CSE2410 Fall 2014 Bounce

// Copyright 2006-2008 the V8 project authors. All rights reserved.

// Redistribution and use in source and binary forms, with or without

// modification, are permitted provided that the following conditions are

// met:

//

//     * Redistributions of source code must retain the above copyright

//       notice, this list of conditions and the following disclaimer.

//     * Redistributions in binary form must reproduce the above

//       copyright notice, this list of conditions and the following

//       disclaimer in the documentation and/or other materials provided

//       with the distribution.

//     * Neither the name of Google Inc. nor the names of its

//       contributors may be used to endorse or promote products derived

//       from this software without specific prior written permission.

//

// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR

// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT

// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,

// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT

// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,

// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY

// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

// CPU specific code for arm independent of OS goes here.

#if defined(__arm__)

#include <sys/syscall.h>  // for cache flushing.

#endif

#include "v8.h"

#include "cpu.h"

namespace v8 { namespace internal {

void CPU::Setup() {

  // Nothing to do.

}

void CPU::FlushICache(void* start, size_t size) {

#if !defined (__arm__)

  // Not generating ARM instructions for C-code. This means that we are

  // building an ARM emulator based target. No I$ flushes are necessary.

#else

  // Ideally, we would call

  //   syscall(__ARM_NR_cacheflush, start,

  //           reinterpret_cast<intptr_t>(start) + size, 0);

  // however, syscall(int, ...) is not supported on all platforms, especially

  // not when using EABI, so we call the __ARM_NR_cacheflush syscall directly.

  register uint32_t beg asm("a1") = reinterpret_cast<uint32_t>(start);

  register uint32_t end asm("a2") =

      reinterpret_cast<uint32_t>(start) + size;

  register uint32_t flg asm("a3") = 0;

  #ifdef __ARM_EABI__

    register uint32_t scno asm("r7") = __ARM_NR_cacheflush;

    #if defined (__arm__) && !defined(__thumb__)

      // __arm__ may be defined in thumb mode.

      asm volatile(

          "swi 0x0"

          : "=r" (beg)

          : "0" (beg), "r" (end), "r" (flg), "r" (scno));

    #else

      asm volatile(

      "@   Enter ARM Mode  \n\t"

          "adr r3, 1f      \n\t"

          "bx  r3          \n\t"

          ".ALIGN 4        \n\t"

          ".ARM            \n"

      "1:  swi 0x0         \n\t"

      "@   Enter THUMB Mode\n\t"

          "adr r3, 2f+1    \n\t"

          "bx  r3          \n\t"

          ".THUMB          \n"

      "2:                  \n\t"

          : "=r" (beg)

          : "0" (beg), "r" (end), "r" (flg), "r" (scno)

          : "r3");

    #endif

  #else

    #if defined (__arm__) && !defined(__thumb__)

      // __arm__ may be defined in thumb mode.

      asm volatile(

          "swi %1"

          : "=r" (beg)

          : "i" (__ARM_NR_cacheflush), "0" (beg), "r" (end), "r" (flg));

    #else

      // Do not use the value of __ARM_NR_cacheflush in the inline assembly

      // below, because the thumb mode value would be used, which would be

      // wrong, since we switch to ARM mode before executing the swi instruction

      asm volatile(

      "@   Enter ARM Mode  \n\t"

          "adr r3, 1f      \n\t"

          "bx  r3          \n\t"

          ".ALIGN 4        \n\t"

          ".ARM            \n"

      "1:  swi 0x9f0002    \n"

      "@   Enter THUMB Mode\n\t"

          "adr r3, 2f+1    \n\t"

          "bx  r3          \n\t"

          ".THUMB          \n"

      "2:                  \n\t"

          : "=r" (beg)

          : "0" (beg), "r" (end), "r" (flg)

          : "r3");

    #endif

  #endif

#endif

}

void CPU::DebugBreak() {

#if !defined (__arm__)

  UNIMPLEMENTED();  // when building ARM emulator target

#else

  asm volatile("bkpt 0");

#endif

}

} }  // namespace v8::internal