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main_repo / deps / v8 / src / disasm-ia32.cc @ 40c0f755
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// Copyright 2007-2008 the V8 project authors. All rights reserved.
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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// * Neither the name of Google Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#include <assert.h> |
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#include <stdio.h> |
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#include <stdarg.h> |
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#include "v8.h" |
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#include "disasm.h" |
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namespace disasm {
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enum OperandOrder {
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UNSET_OP_ORDER = 0,
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REG_OPER_OP_ORDER, |
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OPER_REG_OP_ORDER |
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}; |
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//------------------------------------------------------------------
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// Tables
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//------------------------------------------------------------------
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struct ByteMnemonic {
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int b; // -1 terminates, otherwise must be in range (0..255) |
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const char* mnem; |
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OperandOrder op_order_; |
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}; |
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static ByteMnemonic two_operands_instr[] = {
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{0x03, "add", REG_OPER_OP_ORDER}, |
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{0x21, "and", OPER_REG_OP_ORDER}, |
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{0x23, "and", REG_OPER_OP_ORDER}, |
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{0x3B, "cmp", REG_OPER_OP_ORDER}, |
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{0x8D, "lea", REG_OPER_OP_ORDER}, |
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{0x09, "or", OPER_REG_OP_ORDER}, |
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{0x0B, "or", REG_OPER_OP_ORDER}, |
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{0x1B, "sbb", REG_OPER_OP_ORDER}, |
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{0x29, "sub", OPER_REG_OP_ORDER}, |
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{0x2B, "sub", REG_OPER_OP_ORDER}, |
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{0x85, "test", REG_OPER_OP_ORDER}, |
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{0x31, "xor", OPER_REG_OP_ORDER}, |
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{0x33, "xor", REG_OPER_OP_ORDER}, |
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{0x87, "xchg", REG_OPER_OP_ORDER}, |
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{0x8A, "mov_b", REG_OPER_OP_ORDER}, |
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{0x8B, "mov", REG_OPER_OP_ORDER}, |
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{-1, "", UNSET_OP_ORDER} |
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}; |
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static ByteMnemonic zero_operands_instr[] = {
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{0xC3, "ret", UNSET_OP_ORDER}, |
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{0xC9, "leave", UNSET_OP_ORDER}, |
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{0x90, "nop", UNSET_OP_ORDER}, |
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{0xF4, "hlt", UNSET_OP_ORDER}, |
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{0xCC, "int3", UNSET_OP_ORDER}, |
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{0x60, "pushad", UNSET_OP_ORDER}, |
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{0x61, "popad", UNSET_OP_ORDER}, |
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{0x9C, "pushfd", UNSET_OP_ORDER}, |
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{0x9D, "popfd", UNSET_OP_ORDER}, |
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{0x9E, "sahf", UNSET_OP_ORDER}, |
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{0x99, "cdq", UNSET_OP_ORDER}, |
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{0x9B, "fwait", UNSET_OP_ORDER}, |
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{-1, "", UNSET_OP_ORDER} |
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}; |
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static ByteMnemonic call_jump_instr[] = {
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{0xE8, "call", UNSET_OP_ORDER}, |
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{0xE9, "jmp", UNSET_OP_ORDER}, |
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{-1, "", UNSET_OP_ORDER} |
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}; |
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static ByteMnemonic short_immediate_instr[] = {
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{0x05, "add", UNSET_OP_ORDER}, |
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{0x0D, "or", UNSET_OP_ORDER}, |
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{0x15, "adc", UNSET_OP_ORDER}, |
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{0x25, "and", UNSET_OP_ORDER}, |
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{0x2D, "sub", UNSET_OP_ORDER}, |
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{0x35, "xor", UNSET_OP_ORDER}, |
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{0x3D, "cmp", UNSET_OP_ORDER}, |
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{-1, "", UNSET_OP_ORDER} |
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}; |
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static const char* jump_conditional_mnem[] = { |
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/*0*/ "jo", "jno", "jc", "jnc", |
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/*4*/ "jz", "jnz", "jna", "ja", |
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/*8*/ "js", "jns", "jpe", "jpo", |
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/*12*/ "jl", "jnl", "jng", "jg" |
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}; |
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static const char* set_conditional_mnem[] = { |
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/*0*/ "seto", "setno", "setc", "setnc", |
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/*4*/ "setz", "setnz", "setna", "seta", |
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/*8*/ "sets", "setns", "setpe", "setpo", |
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/*12*/ "setl", "setnl", "setng", "setg" |
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}; |
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enum InstructionType {
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NO_INSTR, |
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ZERO_OPERANDS_INSTR, |
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TWO_OPERANDS_INSTR, |
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JUMP_CONDITIONAL_SHORT_INSTR, |
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REGISTER_INSTR, |
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MOVE_REG_INSTR, |
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CALL_JUMP_INSTR, |
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SHORT_IMMEDIATE_INSTR |
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}; |
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struct InstructionDesc {
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const char* mnem; |
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InstructionType type; |
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OperandOrder op_order_; |
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}; |
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class InstructionTable { |
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public:
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InstructionTable(); |
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const InstructionDesc& Get(byte x) const { return instructions_[x]; } |
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private:
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InstructionDesc instructions_[256];
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void Clear();
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void Init();
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void CopyTable(ByteMnemonic bm[], InstructionType type);
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void SetTableRange(InstructionType type,
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byte start, |
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byte end, |
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const char* mnem); |
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void AddJumpConditionalShort();
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}; |
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InstructionTable::InstructionTable() { |
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Clear(); |
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Init(); |
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} |
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void InstructionTable::Clear() {
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for (int i = 0; i < 256; i++) { |
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instructions_[i].mnem = "";
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instructions_[i].type = NO_INSTR; |
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instructions_[i].op_order_ = UNSET_OP_ORDER; |
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} |
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} |
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void InstructionTable::Init() {
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CopyTable(two_operands_instr, TWO_OPERANDS_INSTR); |
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CopyTable(zero_operands_instr, ZERO_OPERANDS_INSTR); |
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CopyTable(call_jump_instr, CALL_JUMP_INSTR); |
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CopyTable(short_immediate_instr, SHORT_IMMEDIATE_INSTR); |
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AddJumpConditionalShort(); |
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SetTableRange(REGISTER_INSTR, 0x40, 0x47, "inc"); |
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SetTableRange(REGISTER_INSTR, 0x48, 0x4F, "dec"); |
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SetTableRange(REGISTER_INSTR, 0x50, 0x57, "push"); |
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SetTableRange(REGISTER_INSTR, 0x58, 0x5F, "pop"); |
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SetTableRange(REGISTER_INSTR, 0x91, 0x97, "xchg eax,"); // 0x90 is nop. |
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SetTableRange(MOVE_REG_INSTR, 0xB8, 0xBF, "mov"); |
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} |
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void InstructionTable::CopyTable(ByteMnemonic bm[], InstructionType type) {
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for (int i = 0; bm[i].b >= 0; i++) { |
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InstructionDesc* id = &instructions_[bm[i].b]; |
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id->mnem = bm[i].mnem; |
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id->op_order_ = bm[i].op_order_; |
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assert(id->type == NO_INSTR); // Information already entered
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id->type = type; |
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} |
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} |
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void InstructionTable::SetTableRange(InstructionType type,
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byte start, |
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byte end, |
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const char* mnem) { |
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for (byte b = start; b <= end; b++) {
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InstructionDesc* id = &instructions_[b]; |
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assert(id->type == NO_INSTR); // Information already entered
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id->mnem = mnem; |
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id->type = type; |
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} |
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} |
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void InstructionTable::AddJumpConditionalShort() {
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for (byte b = 0x70; b <= 0x7F; b++) { |
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InstructionDesc* id = &instructions_[b]; |
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assert(id->type == NO_INSTR); // Information already entered
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id->mnem = jump_conditional_mnem[b & 0x0F];
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id->type = JUMP_CONDITIONAL_SHORT_INSTR; |
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} |
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} |
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static InstructionTable instruction_table;
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// The IA32 disassembler implementation.
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class DisassemblerIA32 { |
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public:
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DisassemblerIA32(const NameConverter& converter,
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bool abort_on_unimplemented = true) |
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: converter_(converter), |
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tmp_buffer_pos_(0),
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abort_on_unimplemented_(abort_on_unimplemented) { |
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tmp_buffer_[0] = '\0'; |
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} |
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virtual ~DisassemblerIA32() {}
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// Writes one disassembled instruction into 'buffer' (0-terminated).
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// Returns the length of the disassembled machine instruction in bytes.
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int InstructionDecode(v8::internal::Vector<char> buffer, byte* instruction); |
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private:
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const NameConverter& converter_;
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v8::internal::EmbeddedVector<char, 128> tmp_buffer_; |
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unsigned int tmp_buffer_pos_; |
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bool abort_on_unimplemented_;
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enum {
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eax = 0,
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ecx = 1,
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edx = 2,
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ebx = 3,
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esp = 4,
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ebp = 5,
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esi = 6,
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edi = 7
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}; |
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const char* NameOfCPURegister(int reg) const { |
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return converter_.NameOfCPURegister(reg);
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} |
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const char* NameOfByteCPURegister(int reg) const { |
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return converter_.NameOfByteCPURegister(reg);
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} |
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const char* NameOfXMMRegister(int reg) const { |
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return converter_.NameOfXMMRegister(reg);
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} |
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const char* NameOfAddress(byte* addr) const { |
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return converter_.NameOfAddress(addr);
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} |
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// Disassembler helper functions.
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static void get_modrm(byte data, int* mod, int* regop, int* rm) { |
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*mod = (data >> 6) & 3; |
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*regop = (data & 0x38) >> 3; |
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*rm = data & 7;
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} |
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static void get_sib(byte data, int* scale, int* index, int* base) { |
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*scale = (data >> 6) & 3; |
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*index = (data >> 3) & 7; |
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*base = data & 7;
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} |
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typedef const char* (DisassemblerIA32::*RegisterNameMapping)(int reg) const; |
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int PrintRightOperandHelper(byte* modrmp, RegisterNameMapping register_name);
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int PrintRightOperand(byte* modrmp);
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int PrintRightByteOperand(byte* modrmp);
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int PrintOperands(const char* mnem, OperandOrder op_order, byte* data); |
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int PrintImmediateOp(byte* data);
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int F7Instruction(byte* data);
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int D1D3C1Instruction(byte* data);
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int JumpShort(byte* data);
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int JumpConditional(byte* data, const char* comment); |
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int JumpConditionalShort(byte* data, const char* comment); |
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int SetCC(byte* data);
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int FPUInstruction(byte* data);
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void AppendToBuffer(const char* format, ...); |
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void UnimplementedInstruction() {
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if (abort_on_unimplemented_) {
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UNIMPLEMENTED(); |
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} else {
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AppendToBuffer("'Unimplemented Instruction'");
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} |
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} |
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}; |
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void DisassemblerIA32::AppendToBuffer(const char* format, ...) { |
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v8::internal::Vector<char> buf = tmp_buffer_ + tmp_buffer_pos_;
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va_list args; |
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va_start(args, format); |
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int result = v8::internal::OS::VSNPrintF(buf, format, args);
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va_end(args); |
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tmp_buffer_pos_ += result; |
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} |
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int DisassemblerIA32::PrintRightOperandHelper(
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byte* modrmp, |
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RegisterNameMapping register_name) { |
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int mod, regop, rm;
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get_modrm(*modrmp, &mod, ®op, &rm); |
342 |
switch (mod) {
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case 0: |
344 |
if (rm == ebp) {
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int32_t disp = *reinterpret_cast<int32_t*>(modrmp+1); |
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AppendToBuffer("[0x%x]", disp);
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return 5; |
348 |
} else if (rm == esp) { |
349 |
byte sib = *(modrmp + 1);
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int scale, index, base;
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get_sib(sib, &scale, &index, &base); |
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if (index == esp && base == esp && scale == 0 /*times_1*/) { |
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AppendToBuffer("[%s]", (this->*register_name)(rm)); |
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return 2; |
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} else if (base == ebp) { |
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int32_t disp = *reinterpret_cast<int32_t*>(modrmp + 2); |
357 |
AppendToBuffer("[%s*%d+0x%x]",
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(this->*register_name)(index),
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1 << scale,
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disp); |
361 |
return 6; |
362 |
} else if (index != esp && base != ebp) { |
363 |
// [base+index*scale]
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AppendToBuffer("[%s+%s*%d]",
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(this->*register_name)(base),
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(this->*register_name)(index),
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1 << scale);
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return 2; |
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} else {
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UnimplementedInstruction(); |
371 |
return 1; |
372 |
} |
373 |
} else {
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AppendToBuffer("[%s]", (this->*register_name)(rm)); |
375 |
return 1; |
376 |
} |
377 |
break;
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case 1: // fall through |
379 |
case 2: |
380 |
if (rm == esp) {
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byte sib = *(modrmp + 1);
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int scale, index, base;
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get_sib(sib, &scale, &index, &base); |
384 |
int disp =
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mod == 2 ? *reinterpret_cast<int32_t*>(modrmp + 2) : *(modrmp + 2); |
386 |
if (index == base && index == rm /*esp*/ && scale == 0 /*times_1*/) { |
387 |
AppendToBuffer("[%s+0x%x]", (this->*register_name)(rm), disp); |
388 |
} else {
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389 |
AppendToBuffer("[%s+%s*%d+0x%x]",
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390 |
(this->*register_name)(base),
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(this->*register_name)(index),
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1 << scale,
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disp); |
394 |
} |
395 |
return mod == 2 ? 6 : 3; |
396 |
} else {
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397 |
// No sib.
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int disp =
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399 |
mod == 2 ? *reinterpret_cast<int32_t*>(modrmp + 1) : *(modrmp + 1); |
400 |
AppendToBuffer("[%s+0x%x]", (this->*register_name)(rm), disp); |
401 |
return mod == 2 ? 5 : 2; |
402 |
} |
403 |
break;
|
404 |
case 3: |
405 |
AppendToBuffer("%s", (this->*register_name)(rm)); |
406 |
return 1; |
407 |
default:
|
408 |
UnimplementedInstruction(); |
409 |
return 1; |
410 |
} |
411 |
UNREACHABLE(); |
412 |
} |
413 |
|
414 |
|
415 |
int DisassemblerIA32::PrintRightOperand(byte* modrmp) {
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416 |
return PrintRightOperandHelper(modrmp, &DisassemblerIA32::NameOfCPURegister);
|
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} |
418 |
|
419 |
|
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int DisassemblerIA32::PrintRightByteOperand(byte* modrmp) {
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421 |
return PrintRightOperandHelper(modrmp,
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&DisassemblerIA32::NameOfByteCPURegister); |
423 |
} |
424 |
|
425 |
|
426 |
// Returns number of bytes used including the current *data.
|
427 |
// Writes instruction's mnemonic, left and right operands to 'tmp_buffer_'.
|
428 |
int DisassemblerIA32::PrintOperands(const char* mnem, |
429 |
OperandOrder op_order, |
430 |
byte* data) { |
431 |
byte modrm = *data; |
432 |
int mod, regop, rm;
|
433 |
get_modrm(modrm, &mod, ®op, &rm); |
434 |
int advance = 0; |
435 |
switch (op_order) {
|
436 |
case REG_OPER_OP_ORDER: {
|
437 |
AppendToBuffer("%s %s,", mnem, NameOfCPURegister(regop));
|
438 |
advance = PrintRightOperand(data); |
439 |
break;
|
440 |
} |
441 |
case OPER_REG_OP_ORDER: {
|
442 |
AppendToBuffer("%s ", mnem);
|
443 |
advance = PrintRightOperand(data); |
444 |
AppendToBuffer(",%s", NameOfCPURegister(regop));
|
445 |
break;
|
446 |
} |
447 |
default:
|
448 |
UNREACHABLE(); |
449 |
break;
|
450 |
} |
451 |
return advance;
|
452 |
} |
453 |
|
454 |
|
455 |
// Returns number of bytes used by machine instruction, including *data byte.
|
456 |
// Writes immediate instructions to 'tmp_buffer_'.
|
457 |
int DisassemblerIA32::PrintImmediateOp(byte* data) {
|
458 |
bool sign_extension_bit = (*data & 0x02) != 0; |
459 |
byte modrm = *(data+1);
|
460 |
int mod, regop, rm;
|
461 |
get_modrm(modrm, &mod, ®op, &rm); |
462 |
const char* mnem = "Imm???"; |
463 |
switch (regop) {
|
464 |
case 0: mnem = "add"; break; |
465 |
case 1: mnem = "or"; break; |
466 |
case 2: mnem = "adc"; break; |
467 |
case 4: mnem = "and"; break; |
468 |
case 5: mnem = "sub"; break; |
469 |
case 6: mnem = "xor"; break; |
470 |
case 7: mnem = "cmp"; break; |
471 |
default: UnimplementedInstruction();
|
472 |
} |
473 |
AppendToBuffer("%s ", mnem);
|
474 |
int count = PrintRightOperand(data+1); |
475 |
if (sign_extension_bit) {
|
476 |
AppendToBuffer(",0x%x", *(data + 1 + count)); |
477 |
return 1 + count + 1 /*int8*/; |
478 |
} else {
|
479 |
AppendToBuffer(",0x%x", *reinterpret_cast<int32_t*>(data + 1 + count)); |
480 |
return 1 + count + 4 /*int32_t*/; |
481 |
} |
482 |
} |
483 |
|
484 |
|
485 |
// Returns number of bytes used, including *data.
|
486 |
int DisassemblerIA32::F7Instruction(byte* data) {
|
487 |
assert(*data == 0xF7);
|
488 |
byte modrm = *(data+1);
|
489 |
int mod, regop, rm;
|
490 |
get_modrm(modrm, &mod, ®op, &rm); |
491 |
if (mod == 3 && regop != 0) { |
492 |
const char* mnem = NULL; |
493 |
switch (regop) {
|
494 |
case 2: mnem = "not"; break; |
495 |
case 3: mnem = "neg"; break; |
496 |
case 4: mnem = "mul"; break; |
497 |
case 7: mnem = "idiv"; break; |
498 |
default: UnimplementedInstruction();
|
499 |
} |
500 |
AppendToBuffer("%s %s", mnem, NameOfCPURegister(rm));
|
501 |
return 2; |
502 |
} else if (mod == 3 && regop == eax) { |
503 |
int32_t imm = *reinterpret_cast<int32_t*>(data+2); |
504 |
AppendToBuffer("test %s,0x%x", NameOfCPURegister(rm), imm);
|
505 |
return 6; |
506 |
} else if (regop == eax) { |
507 |
AppendToBuffer("test ");
|
508 |
int count = PrintRightOperand(data+1); |
509 |
int32_t imm = *reinterpret_cast<int32_t*>(data+1+count); |
510 |
AppendToBuffer(",0x%x", imm);
|
511 |
return 1+count+4 /*int32_t*/; |
512 |
} else {
|
513 |
UnimplementedInstruction(); |
514 |
return 2; |
515 |
} |
516 |
} |
517 |
|
518 |
int DisassemblerIA32::D1D3C1Instruction(byte* data) {
|
519 |
byte op = *data; |
520 |
assert(op == 0xD1 || op == 0xD3 || op == 0xC1); |
521 |
byte modrm = *(data+1);
|
522 |
int mod, regop, rm;
|
523 |
get_modrm(modrm, &mod, ®op, &rm); |
524 |
int imm8 = -1; |
525 |
int num_bytes = 2; |
526 |
if (mod == 3) { |
527 |
const char* mnem = NULL; |
528 |
if (op == 0xD1) { |
529 |
imm8 = 1;
|
530 |
switch (regop) {
|
531 |
case edx: mnem = "rcl"; break; |
532 |
case edi: mnem = "sar"; break; |
533 |
case esp: mnem = "shl"; break; |
534 |
default: UnimplementedInstruction();
|
535 |
} |
536 |
} else if (op == 0xC1) { |
537 |
imm8 = *(data+2);
|
538 |
num_bytes = 3;
|
539 |
switch (regop) {
|
540 |
case edx: mnem = "rcl"; break; |
541 |
case esp: mnem = "shl"; break; |
542 |
case ebp: mnem = "shr"; break; |
543 |
case edi: mnem = "sar"; break; |
544 |
default: UnimplementedInstruction();
|
545 |
} |
546 |
} else if (op == 0xD3) { |
547 |
switch (regop) {
|
548 |
case esp: mnem = "shl"; break; |
549 |
case ebp: mnem = "shr"; break; |
550 |
case edi: mnem = "sar"; break; |
551 |
default: UnimplementedInstruction();
|
552 |
} |
553 |
} |
554 |
assert(mnem != NULL);
|
555 |
AppendToBuffer("%s %s,", mnem, NameOfCPURegister(rm));
|
556 |
if (imm8 > 0) { |
557 |
AppendToBuffer("%d", imm8);
|
558 |
} else {
|
559 |
AppendToBuffer("cl");
|
560 |
} |
561 |
} else {
|
562 |
UnimplementedInstruction(); |
563 |
} |
564 |
return num_bytes;
|
565 |
} |
566 |
|
567 |
|
568 |
// Returns number of bytes used, including *data.
|
569 |
int DisassemblerIA32::JumpShort(byte* data) {
|
570 |
assert(*data == 0xEB);
|
571 |
byte b = *(data+1);
|
572 |
byte* dest = data + static_cast<int8_t>(b) + 2; |
573 |
AppendToBuffer("jmp %s", NameOfAddress(dest));
|
574 |
return 2; |
575 |
} |
576 |
|
577 |
|
578 |
// Returns number of bytes used, including *data.
|
579 |
int DisassemblerIA32::JumpConditional(byte* data, const char* comment) { |
580 |
assert(*data == 0x0F);
|
581 |
byte cond = *(data+1) & 0x0F; |
582 |
byte* dest = data + *reinterpret_cast<int32_t*>(data+2) + 6; |
583 |
const char* mnem = jump_conditional_mnem[cond]; |
584 |
AppendToBuffer("%s %s", mnem, NameOfAddress(dest));
|
585 |
if (comment != NULL) { |
586 |
AppendToBuffer(", %s", comment);
|
587 |
} |
588 |
return 6; // includes 0x0F |
589 |
} |
590 |
|
591 |
|
592 |
// Returns number of bytes used, including *data.
|
593 |
int DisassemblerIA32::JumpConditionalShort(byte* data, const char* comment) { |
594 |
byte cond = *data & 0x0F;
|
595 |
byte b = *(data+1);
|
596 |
byte* dest = data + static_cast<int8_t>(b) + 2; |
597 |
const char* mnem = jump_conditional_mnem[cond]; |
598 |
AppendToBuffer("%s %s", mnem, NameOfAddress(dest));
|
599 |
if (comment != NULL) { |
600 |
AppendToBuffer(", %s", comment);
|
601 |
} |
602 |
return 2; |
603 |
} |
604 |
|
605 |
|
606 |
// Returns number of bytes used, including *data.
|
607 |
int DisassemblerIA32::SetCC(byte* data) {
|
608 |
assert(*data == 0x0F);
|
609 |
byte cond = *(data+1) & 0x0F; |
610 |
const char* mnem = set_conditional_mnem[cond]; |
611 |
AppendToBuffer("%s ", mnem);
|
612 |
PrintRightByteOperand(data+2);
|
613 |
return 3; // includes 0x0F |
614 |
} |
615 |
|
616 |
|
617 |
// Returns number of bytes used, including *data.
|
618 |
int DisassemblerIA32::FPUInstruction(byte* data) {
|
619 |
byte b1 = *data; |
620 |
byte b2 = *(data + 1);
|
621 |
if (b1 == 0xD9) { |
622 |
const char* mnem = NULL; |
623 |
switch (b2) {
|
624 |
case 0xE8: mnem = "fld1"; break; |
625 |
case 0xEE: mnem = "fldz"; break; |
626 |
case 0xE1: mnem = "fabs"; break; |
627 |
case 0xE0: mnem = "fchs"; break; |
628 |
case 0xF8: mnem = "fprem"; break; |
629 |
case 0xF5: mnem = "fprem1"; break; |
630 |
case 0xF7: mnem = "fincstp"; break; |
631 |
case 0xE4: mnem = "ftst"; break; |
632 |
} |
633 |
if (mnem != NULL) { |
634 |
AppendToBuffer("%s", mnem);
|
635 |
return 2; |
636 |
} else if ((b2 & 0xF8) == 0xC8) { |
637 |
AppendToBuffer("fxch st%d", b2 & 0x7); |
638 |
return 2; |
639 |
} else {
|
640 |
int mod, regop, rm;
|
641 |
get_modrm(*(data+1), &mod, ®op, &rm);
|
642 |
const char* mnem = "?"; |
643 |
switch (regop) {
|
644 |
case eax: mnem = "fld_s"; break; |
645 |
case ebx: mnem = "fstp_s"; break; |
646 |
default: UnimplementedInstruction();
|
647 |
} |
648 |
AppendToBuffer("%s ", mnem);
|
649 |
int count = PrintRightOperand(data + 1); |
650 |
return count + 1; |
651 |
} |
652 |
} else if (b1 == 0xDD) { |
653 |
if ((b2 & 0xF8) == 0xC0) { |
654 |
AppendToBuffer("ffree st%d", b2 & 0x7); |
655 |
return 2; |
656 |
} else {
|
657 |
int mod, regop, rm;
|
658 |
get_modrm(*(data+1), &mod, ®op, &rm);
|
659 |
const char* mnem = "?"; |
660 |
switch (regop) {
|
661 |
case eax: mnem = "fld_d"; break; |
662 |
case ebx: mnem = "fstp_d"; break; |
663 |
default: UnimplementedInstruction();
|
664 |
} |
665 |
AppendToBuffer("%s ", mnem);
|
666 |
int count = PrintRightOperand(data + 1); |
667 |
return count + 1; |
668 |
} |
669 |
} else if (b1 == 0xDB) { |
670 |
int mod, regop, rm;
|
671 |
get_modrm(*(data+1), &mod, ®op, &rm);
|
672 |
const char* mnem = "?"; |
673 |
switch (regop) {
|
674 |
case eax: mnem = "fild_s"; break; |
675 |
case edx: mnem = "fist_s"; break; |
676 |
case ebx: mnem = "fistp_s"; break; |
677 |
default: UnimplementedInstruction();
|
678 |
} |
679 |
AppendToBuffer("%s ", mnem);
|
680 |
int count = PrintRightOperand(data + 1); |
681 |
return count + 1; |
682 |
} else if (b1 == 0xDF) { |
683 |
if (b2 == 0xE0) { |
684 |
AppendToBuffer("fnstsw_ax");
|
685 |
return 2; |
686 |
} |
687 |
int mod, regop, rm;
|
688 |
get_modrm(*(data+1), &mod, ®op, &rm);
|
689 |
const char* mnem = "?"; |
690 |
switch (regop) {
|
691 |
case ebp: mnem = "fild_d"; break; |
692 |
case edi: mnem = "fistp_d"; break; |
693 |
default: UnimplementedInstruction();
|
694 |
} |
695 |
AppendToBuffer("%s ", mnem);
|
696 |
int count = PrintRightOperand(data + 1); |
697 |
return count + 1; |
698 |
} else if (b1 == 0xDC || b1 == 0xDE) { |
699 |
bool is_pop = (b1 == 0xDE); |
700 |
if (is_pop && b2 == 0xD9) { |
701 |
AppendToBuffer("fcompp");
|
702 |
return 2; |
703 |
} |
704 |
const char* mnem = "FP0xDC"; |
705 |
switch (b2 & 0xF8) { |
706 |
case 0xC0: mnem = "fadd"; break; |
707 |
case 0xE8: mnem = "fsub"; break; |
708 |
case 0xC8: mnem = "fmul"; break; |
709 |
case 0xF8: mnem = "fdiv"; break; |
710 |
default: UnimplementedInstruction();
|
711 |
} |
712 |
AppendToBuffer("%s%s st%d", mnem, is_pop ? "p" : "", b2 & 0x7); |
713 |
return 2; |
714 |
} else if (b1 == 0xDA && b2 == 0xE9) { |
715 |
const char* mnem = "fucompp"; |
716 |
AppendToBuffer("%s", mnem);
|
717 |
return 2; |
718 |
} |
719 |
AppendToBuffer("Unknown FP instruction");
|
720 |
return 2; |
721 |
} |
722 |
|
723 |
|
724 |
// Mnemonics for instructions 0xF0 byte.
|
725 |
// Returns NULL if the instruction is not handled here.
|
726 |
static const char* F0Mnem(byte f0byte) { |
727 |
switch (f0byte) {
|
728 |
case 0xA2: return "cpuid"; |
729 |
case 0x31: return "rdtsc"; |
730 |
case 0xBE: return "movsx_b"; |
731 |
case 0xBF: return "movsx_w"; |
732 |
case 0xB6: return "movzx_b"; |
733 |
case 0xB7: return "movzx_w"; |
734 |
case 0xAF: return "imul"; |
735 |
case 0xA5: return "shld"; |
736 |
case 0xAD: return "shrd"; |
737 |
case 0xAB: return "bts"; |
738 |
default: return NULL; |
739 |
} |
740 |
} |
741 |
|
742 |
|
743 |
// Disassembled instruction '*instr' and writes it into 'out_buffer'.
|
744 |
int DisassemblerIA32::InstructionDecode(v8::internal::Vector<char> out_buffer, |
745 |
byte* instr) { |
746 |
tmp_buffer_pos_ = 0; // starting to write as position 0 |
747 |
byte* data = instr; |
748 |
// Check for hints.
|
749 |
const char* branch_hint = NULL; |
750 |
// We use these two prefixes only with branch prediction
|
751 |
if (*data == 0x3E /*ds*/) { |
752 |
branch_hint = "predicted taken";
|
753 |
data++; |
754 |
} else if (*data == 0x2E /*cs*/) { |
755 |
branch_hint = "predicted not taken";
|
756 |
data++; |
757 |
} |
758 |
bool processed = true; // Will be set to false if the current instruction |
759 |
// is not in 'instructions' table.
|
760 |
const InstructionDesc& idesc = instruction_table.Get(*data);
|
761 |
switch (idesc.type) {
|
762 |
case ZERO_OPERANDS_INSTR:
|
763 |
AppendToBuffer(idesc.mnem); |
764 |
data++; |
765 |
break;
|
766 |
|
767 |
case TWO_OPERANDS_INSTR:
|
768 |
data++; |
769 |
data += PrintOperands(idesc.mnem, idesc.op_order_, data); |
770 |
break;
|
771 |
|
772 |
case JUMP_CONDITIONAL_SHORT_INSTR:
|
773 |
data += JumpConditionalShort(data, branch_hint); |
774 |
break;
|
775 |
|
776 |
case REGISTER_INSTR:
|
777 |
AppendToBuffer("%s %s", idesc.mnem, NameOfCPURegister(*data & 0x07)); |
778 |
data++; |
779 |
break;
|
780 |
|
781 |
case MOVE_REG_INSTR: {
|
782 |
byte* addr = reinterpret_cast<byte*>(*reinterpret_cast<int32_t*>(data+1)); |
783 |
AppendToBuffer("mov %s,%s",
|
784 |
NameOfCPURegister(*data & 0x07),
|
785 |
NameOfAddress(addr)); |
786 |
data += 5;
|
787 |
break;
|
788 |
} |
789 |
|
790 |
case CALL_JUMP_INSTR: {
|
791 |
byte* addr = data + *reinterpret_cast<int32_t*>(data+1) + 5; |
792 |
AppendToBuffer("%s %s", idesc.mnem, NameOfAddress(addr));
|
793 |
data += 5;
|
794 |
break;
|
795 |
} |
796 |
|
797 |
case SHORT_IMMEDIATE_INSTR: {
|
798 |
byte* addr = reinterpret_cast<byte*>(*reinterpret_cast<int32_t*>(data+1)); |
799 |
AppendToBuffer("%s eax, %s", idesc.mnem, NameOfAddress(addr));
|
800 |
data += 5;
|
801 |
break;
|
802 |
} |
803 |
|
804 |
case NO_INSTR:
|
805 |
processed = false;
|
806 |
break;
|
807 |
|
808 |
default:
|
809 |
UNIMPLEMENTED(); // This type is not implemented.
|
810 |
} |
811 |
//----------------------------
|
812 |
if (!processed) {
|
813 |
switch (*data) {
|
814 |
case 0xC2: |
815 |
AppendToBuffer("ret 0x%x", *reinterpret_cast<uint16_t*>(data+1)); |
816 |
data += 3;
|
817 |
break;
|
818 |
|
819 |
case 0x69: // fall through |
820 |
case 0x6B: |
821 |
{ int mod, regop, rm;
|
822 |
get_modrm(*(data+1), &mod, ®op, &rm);
|
823 |
int32_t imm = |
824 |
*data == 0x6B ? *(data+2) : *reinterpret_cast<int32_t*>(data+2); |
825 |
AppendToBuffer("imul %s,%s,0x%x",
|
826 |
NameOfCPURegister(regop), |
827 |
NameOfCPURegister(rm), |
828 |
imm); |
829 |
data += 2 + (*data == 0x6B ? 1 : 4); |
830 |
} |
831 |
break;
|
832 |
|
833 |
case 0xF6: |
834 |
{ int mod, regop, rm;
|
835 |
get_modrm(*(data+1), &mod, ®op, &rm);
|
836 |
if (mod == 3 && regop == eax) { |
837 |
AppendToBuffer("test_b %s,%d", NameOfCPURegister(rm), *(data+2)); |
838 |
} else {
|
839 |
UnimplementedInstruction(); |
840 |
} |
841 |
data += 3;
|
842 |
} |
843 |
break;
|
844 |
|
845 |
case 0x81: // fall through |
846 |
case 0x83: // 0x81 with sign extension bit set |
847 |
data += PrintImmediateOp(data); |
848 |
break;
|
849 |
|
850 |
case 0x0F: |
851 |
{ byte f0byte = *(data+1);
|
852 |
const char* f0mnem = F0Mnem(f0byte); |
853 |
if (f0byte == 0xA2 || f0byte == 0x31) { |
854 |
AppendToBuffer("%s", f0mnem);
|
855 |
data += 2;
|
856 |
} else if ((f0byte & 0xF0) == 0x80) { |
857 |
data += JumpConditional(data, branch_hint); |
858 |
} else if (f0byte == 0xBE || f0byte == 0xBF || f0byte == 0xB6 || |
859 |
f0byte == 0xB7 || f0byte == 0xAF) { |
860 |
data += 2;
|
861 |
data += PrintOperands(f0mnem, REG_OPER_OP_ORDER, data); |
862 |
} else if ((f0byte & 0xF0) == 0x90) { |
863 |
data += SetCC(data); |
864 |
} else {
|
865 |
data += 2;
|
866 |
if (f0byte == 0xAB || f0byte == 0xA5 || f0byte == 0xAD) { |
867 |
// shrd, shld, bts
|
868 |
AppendToBuffer("%s ", f0mnem);
|
869 |
int mod, regop, rm;
|
870 |
get_modrm(*data, &mod, ®op, &rm); |
871 |
data += PrintRightOperand(data); |
872 |
if (f0byte == 0xAB) { |
873 |
AppendToBuffer(",%s", NameOfCPURegister(regop));
|
874 |
} else {
|
875 |
AppendToBuffer(",%s,cl", NameOfCPURegister(regop));
|
876 |
} |
877 |
} else {
|
878 |
UnimplementedInstruction(); |
879 |
} |
880 |
} |
881 |
} |
882 |
break;
|
883 |
|
884 |
case 0x8F: |
885 |
{ data++; |
886 |
int mod, regop, rm;
|
887 |
get_modrm(*data, &mod, ®op, &rm); |
888 |
if (regop == eax) {
|
889 |
AppendToBuffer("pop ");
|
890 |
data += PrintRightOperand(data); |
891 |
} |
892 |
} |
893 |
break;
|
894 |
|
895 |
case 0xFF: |
896 |
{ data++; |
897 |
int mod, regop, rm;
|
898 |
get_modrm(*data, &mod, ®op, &rm); |
899 |
const char* mnem = NULL; |
900 |
switch (regop) {
|
901 |
case esi: mnem = "push"; break; |
902 |
case eax: mnem = "inc"; break; |
903 |
case ecx: mnem = "dec"; break; |
904 |
case edx: mnem = "call"; break; |
905 |
case esp: mnem = "jmp"; break; |
906 |
default: mnem = "???"; |
907 |
} |
908 |
AppendToBuffer("%s ", mnem);
|
909 |
data += PrintRightOperand(data); |
910 |
} |
911 |
break;
|
912 |
|
913 |
case 0xC7: // imm32, fall through |
914 |
case 0xC6: // imm8 |
915 |
{ bool is_byte = *data == 0xC6; |
916 |
data++; |
917 |
AppendToBuffer("%s ", is_byte ? "mov_b" : "mov"); |
918 |
data += PrintRightOperand(data); |
919 |
int32_t imm = is_byte ? *data : *reinterpret_cast<int32_t*>(data);
|
920 |
AppendToBuffer(",0x%x", imm);
|
921 |
data += is_byte ? 1 : 4; |
922 |
} |
923 |
break;
|
924 |
|
925 |
case 0x80: |
926 |
{ data++; |
927 |
AppendToBuffer("%s ", "cmpb"); |
928 |
data += PrintRightOperand(data); |
929 |
int32_t imm = *data; |
930 |
AppendToBuffer(",0x%x", imm);
|
931 |
data++; |
932 |
} |
933 |
break;
|
934 |
|
935 |
case 0x88: // 8bit, fall through |
936 |
case 0x89: // 32bit |
937 |
{ bool is_byte = *data == 0x88; |
938 |
int mod, regop, rm;
|
939 |
data++; |
940 |
get_modrm(*data, &mod, ®op, &rm); |
941 |
AppendToBuffer("%s ", is_byte ? "mov_b" : "mov"); |
942 |
data += PrintRightOperand(data); |
943 |
AppendToBuffer(",%s", NameOfCPURegister(regop));
|
944 |
} |
945 |
break;
|
946 |
|
947 |
case 0x66: // prefix |
948 |
data++; |
949 |
if (*data == 0x8B) { |
950 |
data++; |
951 |
data += PrintOperands("mov_w", REG_OPER_OP_ORDER, data);
|
952 |
} else if (*data == 0x89) { |
953 |
data++; |
954 |
int mod, regop, rm;
|
955 |
get_modrm(*data, &mod, ®op, &rm); |
956 |
AppendToBuffer("mov_w ");
|
957 |
data += PrintRightOperand(data); |
958 |
AppendToBuffer(",%s", NameOfCPURegister(regop));
|
959 |
} else {
|
960 |
UnimplementedInstruction(); |
961 |
} |
962 |
break;
|
963 |
|
964 |
case 0xFE: |
965 |
{ data++; |
966 |
int mod, regop, rm;
|
967 |
get_modrm(*data, &mod, ®op, &rm); |
968 |
if (mod == 3 && regop == ecx) { |
969 |
AppendToBuffer("dec_b %s", NameOfCPURegister(rm));
|
970 |
} else {
|
971 |
UnimplementedInstruction(); |
972 |
} |
973 |
data++; |
974 |
} |
975 |
break;
|
976 |
|
977 |
case 0x68: |
978 |
AppendToBuffer("push 0x%x", *reinterpret_cast<int32_t*>(data+1)); |
979 |
data += 5;
|
980 |
break;
|
981 |
|
982 |
case 0x6A: |
983 |
AppendToBuffer("push 0x%x", *reinterpret_cast<int8_t*>(data + 1)); |
984 |
data += 2;
|
985 |
break;
|
986 |
|
987 |
case 0xA8: |
988 |
AppendToBuffer("test al,0x%x", *reinterpret_cast<uint8_t*>(data+1)); |
989 |
data += 2;
|
990 |
break;
|
991 |
|
992 |
case 0xA9: |
993 |
AppendToBuffer("test eax,0x%x", *reinterpret_cast<int32_t*>(data+1)); |
994 |
data += 5;
|
995 |
break;
|
996 |
|
997 |
case 0xD1: // fall through |
998 |
case 0xD3: // fall through |
999 |
case 0xC1: |
1000 |
data += D1D3C1Instruction(data); |
1001 |
break;
|
1002 |
|
1003 |
case 0xD9: // fall through |
1004 |
case 0xDA: // fall through |
1005 |
case 0xDB: // fall through |
1006 |
case 0xDC: // fall through |
1007 |
case 0xDD: // fall through |
1008 |
case 0xDE: // fall through |
1009 |
case 0xDF: |
1010 |
data += FPUInstruction(data); |
1011 |
break;
|
1012 |
|
1013 |
case 0xEB: |
1014 |
data += JumpShort(data); |
1015 |
break;
|
1016 |
|
1017 |
case 0xF2: |
1018 |
if (*(data+1) == 0x0F) { |
1019 |
byte b2 = *(data+2);
|
1020 |
if (b2 == 0x11) { |
1021 |
AppendToBuffer("movsd ");
|
1022 |
data += 3;
|
1023 |
int mod, regop, rm;
|
1024 |
get_modrm(*data, &mod, ®op, &rm); |
1025 |
data += PrintRightOperand(data); |
1026 |
AppendToBuffer(",%s", NameOfXMMRegister(regop));
|
1027 |
} else if (b2 == 0x10) { |
1028 |
data += 3;
|
1029 |
int mod, regop, rm;
|
1030 |
get_modrm(*data, &mod, ®op, &rm); |
1031 |
AppendToBuffer("movsd %s,", NameOfXMMRegister(regop));
|
1032 |
data += PrintRightOperand(data); |
1033 |
} else {
|
1034 |
const char* mnem = "?"; |
1035 |
switch (b2) {
|
1036 |
case 0x2A: mnem = "cvtsi2sd"; break; |
1037 |
case 0x58: mnem = "addsd"; break; |
1038 |
case 0x59: mnem = "mulsd"; break; |
1039 |
case 0x5C: mnem = "subsd"; break; |
1040 |
case 0x5E: mnem = "divsd"; break; |
1041 |
} |
1042 |
data += 3;
|
1043 |
int mod, regop, rm;
|
1044 |
get_modrm(*data, &mod, ®op, &rm); |
1045 |
if (b2 == 0x2A) { |
1046 |
AppendToBuffer("%s %s,", mnem, NameOfXMMRegister(regop));
|
1047 |
data += PrintRightOperand(data); |
1048 |
} else {
|
1049 |
AppendToBuffer("%s %s,%s",
|
1050 |
mnem, |
1051 |
NameOfXMMRegister(regop), |
1052 |
NameOfXMMRegister(rm)); |
1053 |
data++; |
1054 |
} |
1055 |
} |
1056 |
} else {
|
1057 |
UnimplementedInstruction(); |
1058 |
} |
1059 |
break;
|
1060 |
|
1061 |
case 0xF3: |
1062 |
if (*(data+1) == 0x0F && *(data+2) == 0x2C) { |
1063 |
data += 3;
|
1064 |
data += PrintOperands("cvttss2si", REG_OPER_OP_ORDER, data);
|
1065 |
} else {
|
1066 |
UnimplementedInstruction(); |
1067 |
} |
1068 |
break;
|
1069 |
|
1070 |
case 0xF7: |
1071 |
data += F7Instruction(data); |
1072 |
break;
|
1073 |
|
1074 |
default:
|
1075 |
UnimplementedInstruction(); |
1076 |
} |
1077 |
} |
1078 |
|
1079 |
if (tmp_buffer_pos_ < sizeof tmp_buffer_) { |
1080 |
tmp_buffer_[tmp_buffer_pos_] = '\0';
|
1081 |
} |
1082 |
|
1083 |
int instr_len = data - instr;
|
1084 |
ASSERT(instr_len > 0); // Ensure progress. |
1085 |
|
1086 |
int outp = 0; |
1087 |
// Instruction bytes.
|
1088 |
for (byte* bp = instr; bp < data; bp++) {
|
1089 |
outp += v8::internal::OS::SNPrintF(out_buffer + outp, |
1090 |
"%02x",
|
1091 |
*bp); |
1092 |
} |
1093 |
for (int i = 6 - instr_len; i >= 0; i--) { |
1094 |
outp += v8::internal::OS::SNPrintF(out_buffer + outp, |
1095 |
" ");
|
1096 |
} |
1097 |
|
1098 |
outp += v8::internal::OS::SNPrintF(out_buffer + outp, |
1099 |
" %s",
|
1100 |
tmp_buffer_.start()); |
1101 |
return instr_len;
|
1102 |
} |
1103 |
|
1104 |
|
1105 |
//------------------------------------------------------------------------------
|
1106 |
|
1107 |
|
1108 |
static const char* cpu_regs[8] = { |
1109 |
"eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi" |
1110 |
}; |
1111 |
|
1112 |
|
1113 |
static const char* byte_cpu_regs[8] = { |
1114 |
"al", "cl", "dl", "bl", "ah", "ch", "dh", "bh" |
1115 |
}; |
1116 |
|
1117 |
|
1118 |
static const char* xmm_regs[8] = { |
1119 |
"xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7" |
1120 |
}; |
1121 |
|
1122 |
|
1123 |
const char* NameConverter::NameOfAddress(byte* addr) const { |
1124 |
static v8::internal::EmbeddedVector<char, 32> tmp_buffer; |
1125 |
v8::internal::OS::SNPrintF(tmp_buffer, "%p", addr);
|
1126 |
return tmp_buffer.start();
|
1127 |
} |
1128 |
|
1129 |
|
1130 |
const char* NameConverter::NameOfConstant(byte* addr) const { |
1131 |
return NameOfAddress(addr);
|
1132 |
} |
1133 |
|
1134 |
|
1135 |
const char* NameConverter::NameOfCPURegister(int reg) const { |
1136 |
if (0 <= reg && reg < 8) return cpu_regs[reg]; |
1137 |
return "noreg"; |
1138 |
} |
1139 |
|
1140 |
|
1141 |
const char* NameConverter::NameOfByteCPURegister(int reg) const { |
1142 |
if (0 <= reg && reg < 8) return byte_cpu_regs[reg]; |
1143 |
return "noreg"; |
1144 |
} |
1145 |
|
1146 |
|
1147 |
const char* NameConverter::NameOfXMMRegister(int reg) const { |
1148 |
if (0 <= reg && reg < 8) return xmm_regs[reg]; |
1149 |
return "noxmmreg"; |
1150 |
} |
1151 |
|
1152 |
|
1153 |
const char* NameConverter::NameInCode(byte* addr) const { |
1154 |
// IA32 does not embed debug strings at the moment.
|
1155 |
UNREACHABLE(); |
1156 |
return ""; |
1157 |
} |
1158 |
|
1159 |
|
1160 |
//------------------------------------------------------------------------------
|
1161 |
|
1162 |
Disassembler::Disassembler(const NameConverter& converter)
|
1163 |
: converter_(converter) {} |
1164 |
|
1165 |
|
1166 |
Disassembler::~Disassembler() {} |
1167 |
|
1168 |
|
1169 |
int Disassembler::InstructionDecode(v8::internal::Vector<char> buffer, |
1170 |
byte* instruction) { |
1171 |
DisassemblerIA32 d(converter_, false /*do not crash if unimplemented*/); |
1172 |
return d.InstructionDecode(buffer, instruction);
|
1173 |
} |
1174 |
|
1175 |
|
1176 |
// The IA-32 assembler does not currently use constant pools.
|
1177 |
int Disassembler::ConstantPoolSizeAt(byte* instruction) { return -1; } |
1178 |
|
1179 |
|
1180 |
/*static*/ void Disassembler::Disassemble(FILE* f, byte* begin, byte* end) { |
1181 |
NameConverter converter; |
1182 |
Disassembler d(converter); |
1183 |
for (byte* pc = begin; pc < end;) {
|
1184 |
v8::internal::EmbeddedVector<char, 128> buffer; |
1185 |
buffer[0] = '\0'; |
1186 |
byte* prev_pc = pc; |
1187 |
pc += d.InstructionDecode(buffer, pc); |
1188 |
fprintf(f, "%p", prev_pc);
|
1189 |
fprintf(f, " ");
|
1190 |
|
1191 |
for (byte* bp = prev_pc; bp < pc; bp++) {
|
1192 |
fprintf(f, "%02x", *bp);
|
1193 |
} |
1194 |
for (int i = 6 - (pc - prev_pc); i >= 0; i--) { |
1195 |
fprintf(f, " ");
|
1196 |
} |
1197 |
fprintf(f, " %s\n", buffer.start());
|
1198 |
} |
1199 |
} |
1200 |
|
1201 |
|
1202 |
} // namespace disasm
|