Revision f230a1cf deps/v8/src/ia32/assembler-ia32.cc
| deps/v8/src/ia32/assembler-ia32.cc | ||
|---|---|---|
| 53 | 53 |
#endif |
| 54 | 54 |
uint64_t CpuFeatures::supported_ = 0; |
| 55 | 55 |
uint64_t CpuFeatures::found_by_runtime_probing_only_ = 0; |
| 56 |
uint64_t CpuFeatures::cross_compile_ = 0; |
|
| 56 | 57 |
|
| 57 | 58 |
|
| 58 | 59 |
ExternalReference ExternalReference::cpu_features() {
|
| ... | ... | |
| 1131 | 1132 |
|
| 1132 | 1133 |
|
| 1133 | 1134 |
void Assembler::test(Register reg, const Immediate& imm) {
|
| 1135 |
if (RelocInfo::IsNone(imm.rmode_) && is_uint8(imm.x_)) {
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| 1136 |
test_b(reg, imm.x_); |
|
| 1137 |
return; |
|
| 1138 |
} |
|
| 1139 |
|
|
| 1134 | 1140 |
EnsureSpace ensure_space(this); |
| 1135 |
// Only use test against byte for registers that have a byte |
|
| 1136 |
// variant: eax, ebx, ecx, and edx. |
|
| 1137 |
if (RelocInfo::IsNone(imm.rmode_) && |
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| 1138 |
is_uint8(imm.x_) && |
|
| 1139 |
reg.is_byte_register()) {
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|
| 1140 |
uint8_t imm8 = imm.x_; |
|
| 1141 |
if (reg.is(eax)) {
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|
| 1142 |
EMIT(0xA8); |
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| 1143 |
EMIT(imm8); |
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| 1144 |
} else {
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|
| 1145 |
emit_arith_b(0xF6, 0xC0, reg, imm8); |
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| 1146 |
} |
|
| 1141 |
// This is not using emit_arith because test doesn't support |
|
| 1142 |
// sign-extension of 8-bit operands. |
|
| 1143 |
if (reg.is(eax)) {
|
|
| 1144 |
EMIT(0xA9); |
|
| 1147 | 1145 |
} else {
|
| 1148 |
// This is not using emit_arith because test doesn't support |
|
| 1149 |
// sign-extension of 8-bit operands. |
|
| 1150 |
if (reg.is(eax)) {
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|
| 1151 |
EMIT(0xA9); |
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| 1152 |
} else {
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|
| 1153 |
EMIT(0xF7); |
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| 1154 |
EMIT(0xC0 | reg.code()); |
|
| 1155 |
} |
|
| 1156 |
emit(imm); |
|
| 1146 |
EMIT(0xF7); |
|
| 1147 |
EMIT(0xC0 | reg.code()); |
|
| 1157 | 1148 |
} |
| 1149 |
emit(imm); |
|
| 1158 | 1150 |
} |
| 1159 | 1151 |
|
| 1160 | 1152 |
|
| ... | ... | |
| 1178 | 1170 |
test(op.reg(), imm); |
| 1179 | 1171 |
return; |
| 1180 | 1172 |
} |
| 1173 |
if (RelocInfo::IsNone(imm.rmode_) && is_uint8(imm.x_)) {
|
|
| 1174 |
return test_b(op, imm.x_); |
|
| 1175 |
} |
|
| 1181 | 1176 |
EnsureSpace ensure_space(this); |
| 1182 | 1177 |
EMIT(0xF7); |
| 1183 | 1178 |
emit_operand(eax, op); |
| ... | ... | |
| 1185 | 1180 |
} |
| 1186 | 1181 |
|
| 1187 | 1182 |
|
| 1183 |
void Assembler::test_b(Register reg, uint8_t imm8) {
|
|
| 1184 |
EnsureSpace ensure_space(this); |
|
| 1185 |
// Only use test against byte for registers that have a byte |
|
| 1186 |
// variant: eax, ebx, ecx, and edx. |
|
| 1187 |
if (reg.is(eax)) {
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|
| 1188 |
EMIT(0xA8); |
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| 1189 |
EMIT(imm8); |
|
| 1190 |
} else if (reg.is_byte_register()) {
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| 1191 |
emit_arith_b(0xF6, 0xC0, reg, imm8); |
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| 1192 |
} else {
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| 1193 |
EMIT(0xF7); |
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| 1194 |
EMIT(0xC0 | reg.code()); |
|
| 1195 |
emit(imm8); |
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| 1196 |
} |
|
| 1197 |
} |
|
| 1198 |
|
|
| 1199 |
|
|
| 1188 | 1200 |
void Assembler::test_b(const Operand& op, uint8_t imm8) {
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| 1189 |
if (op.is_reg_only() && !op.reg().is_byte_register()) {
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| 1190 |
test(op, Immediate(imm8));
|
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| 1201 |
if (op.is_reg_only()) {
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| 1202 |
test_b(op.reg(), imm8);
|
|
| 1191 | 1203 |
return; |
| 1192 | 1204 |
} |
| 1193 | 1205 |
EnsureSpace ensure_space(this); |
| ... | ... | |
| 1402 | 1414 |
TypeFeedbackId ast_id) {
|
| 1403 | 1415 |
positions_recorder()->WriteRecordedPositions(); |
| 1404 | 1416 |
EnsureSpace ensure_space(this); |
| 1405 |
ASSERT(RelocInfo::IsCodeTarget(rmode)); |
|
| 1417 |
ASSERT(RelocInfo::IsCodeTarget(rmode) |
|
| 1418 |
|| rmode == RelocInfo::CODE_AGE_SEQUENCE); |
|
| 1406 | 1419 |
EMIT(0xE8); |
| 1407 | 1420 |
emit(code, rmode, ast_id); |
| 1408 | 1421 |
} |
| ... | ... | |
| 2055 | 2068 |
|
| 2056 | 2069 |
|
| 2057 | 2070 |
void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
|
| 2071 |
ASSERT(IsEnabled(SSE2)); |
|
| 2058 | 2072 |
EnsureSpace ensure_space(this); |
| 2059 | 2073 |
EMIT(0xF2); |
| 2060 | 2074 |
EMIT(0x0F); |
| ... | ... | |
| 2064 | 2078 |
|
| 2065 | 2079 |
|
| 2066 | 2080 |
void Assembler::andpd(XMMRegister dst, XMMRegister src) {
|
| 2081 |
ASSERT(IsEnabled(SSE2)); |
|
| 2067 | 2082 |
EnsureSpace ensure_space(this); |
| 2068 | 2083 |
EMIT(0x66); |
| 2069 | 2084 |
EMIT(0x0F); |
| ... | ... | |
| 2073 | 2088 |
|
| 2074 | 2089 |
|
| 2075 | 2090 |
void Assembler::orpd(XMMRegister dst, XMMRegister src) {
|
| 2091 |
ASSERT(IsEnabled(SSE2)); |
|
| 2076 | 2092 |
EnsureSpace ensure_space(this); |
| 2077 | 2093 |
EMIT(0x66); |
| 2078 | 2094 |
EMIT(0x0F); |
| ... | ... | |
| 2235 | 2251 |
} |
| 2236 | 2252 |
|
| 2237 | 2253 |
|
| 2238 |
void Assembler::movdbl(XMMRegister dst, const Operand& src) {
|
|
| 2239 |
EnsureSpace ensure_space(this); |
|
| 2240 |
movsd(dst, src); |
|
| 2241 |
} |
|
| 2242 |
|
|
| 2243 |
|
|
| 2244 |
void Assembler::movdbl(const Operand& dst, XMMRegister src) {
|
|
| 2245 |
EnsureSpace ensure_space(this); |
|
| 2246 |
movsd(dst, src); |
|
| 2247 |
} |
|
| 2248 |
|
|
| 2249 |
|
|
| 2250 | 2254 |
void Assembler::movsd(const Operand& dst, XMMRegister src ) {
|
| 2251 | 2255 |
ASSERT(IsEnabled(SSE2)); |
| 2252 | 2256 |
EnsureSpace ensure_space(this); |
| ... | ... | |
| 2335 | 2339 |
EMIT(0x0F); |
| 2336 | 2340 |
EMIT(0x3A); |
| 2337 | 2341 |
EMIT(0x17); |
| 2338 |
emit_sse_operand(dst, src);
|
|
| 2342 |
emit_sse_operand(src, dst);
|
|
| 2339 | 2343 |
EMIT(imm8); |
| 2340 | 2344 |
} |
| 2341 | 2345 |
|
| 2342 | 2346 |
|
| 2347 |
void Assembler::andps(XMMRegister dst, XMMRegister src) {
|
|
| 2348 |
EnsureSpace ensure_space(this); |
|
| 2349 |
EMIT(0x0F); |
|
| 2350 |
EMIT(0x54); |
|
| 2351 |
emit_sse_operand(dst, src); |
|
| 2352 |
} |
|
| 2353 |
|
|
| 2354 |
|
|
| 2343 | 2355 |
void Assembler::pand(XMMRegister dst, XMMRegister src) {
|
| 2344 | 2356 |
ASSERT(IsEnabled(SSE2)); |
| 2345 | 2357 |
EnsureSpace ensure_space(this); |
| ... | ... | |
| 2474 | 2486 |
} |
| 2475 | 2487 |
|
| 2476 | 2488 |
|
| 2489 |
void Assembler::emit_sse_operand(XMMRegister dst, Register src) {
|
|
| 2490 |
EMIT(0xC0 | (dst.code() << 3) | src.code()); |
|
| 2491 |
} |
|
| 2492 |
|
|
| 2493 |
|
|
| 2477 | 2494 |
void Assembler::Print() {
|
| 2478 | 2495 |
Disassembler::Decode(isolate(), stdout, buffer_, pc_); |
| 2479 | 2496 |
} |
Also available in: Unified diff