Revision f230a1cf deps/v8/src/lithium-allocator.cc
deps/v8/src/lithium-allocator.cc | ||
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131 | 131 |
LiveRange::LiveRange(int id, Zone* zone) |
132 | 132 |
: id_(id), |
133 | 133 |
spilled_(false), |
134 |
is_double_(false),
|
|
134 |
kind_(UNALLOCATED_REGISTERS),
|
|
135 | 135 |
assigned_register_(kInvalidAssignment), |
136 | 136 |
last_interval_(NULL), |
137 | 137 |
first_interval_(NULL), |
... | ... | |
145 | 145 |
spill_start_index_(kMaxInt) { } |
146 | 146 |
|
147 | 147 |
|
148 |
void LiveRange::set_assigned_register(int reg, |
|
149 |
RegisterKind register_kind, |
|
150 |
Zone* zone) { |
|
148 |
void LiveRange::set_assigned_register(int reg, Zone* zone) { |
|
151 | 149 |
ASSERT(!HasRegisterAssigned() && !IsSpilled()); |
152 | 150 |
assigned_register_ = reg; |
153 |
is_double_ = (register_kind == DOUBLE_REGISTERS); |
|
154 | 151 |
ConvertOperands(zone); |
155 | 152 |
} |
156 | 153 |
|
... | ... | |
234 | 231 |
LOperand* op = NULL; |
235 | 232 |
if (HasRegisterAssigned()) { |
236 | 233 |
ASSERT(!IsSpilled()); |
237 |
if (IsDouble()) { |
|
238 |
op = LDoubleRegister::Create(assigned_register(), zone); |
|
239 |
} else { |
|
240 |
op = LRegister::Create(assigned_register(), zone); |
|
234 |
switch (Kind()) { |
|
235 |
case GENERAL_REGISTERS: |
|
236 |
op = LRegister::Create(assigned_register(), zone); |
|
237 |
break; |
|
238 |
case DOUBLE_REGISTERS: |
|
239 |
op = LDoubleRegister::Create(assigned_register(), zone); |
|
240 |
break; |
|
241 |
default: |
|
242 |
UNREACHABLE(); |
|
241 | 243 |
} |
242 | 244 |
} else if (IsSpilled()) { |
243 | 245 |
ASSERT(!HasRegisterAssigned()); |
... | ... | |
352 | 354 |
// Link the new live range in the chain before any of the other |
353 | 355 |
// ranges linked from the range before the split. |
354 | 356 |
result->parent_ = (parent_ == NULL) ? this : parent_; |
357 |
result->kind_ = result->parent_->kind_; |
|
355 | 358 |
result->next_ = next_; |
356 | 359 |
next_ = result; |
357 | 360 |
|
... | ... | |
553 | 556 |
reusable_slots_(8, zone()), |
554 | 557 |
next_virtual_register_(num_values), |
555 | 558 |
first_artificial_register_(num_values), |
556 |
mode_(GENERAL_REGISTERS),
|
|
559 |
mode_(UNALLOCATED_REGISTERS),
|
|
557 | 560 |
num_registers_(-1), |
558 | 561 |
graph_(graph), |
559 | 562 |
has_osr_entry_(false), |
... | ... | |
653 | 656 |
if (result == NULL) { |
654 | 657 |
result = new(zone()) LiveRange(FixedLiveRangeID(index), chunk()->zone()); |
655 | 658 |
ASSERT(result->IsFixed()); |
656 |
SetLiveRangeAssignedRegister(result, index, GENERAL_REGISTERS); |
|
659 |
result->kind_ = GENERAL_REGISTERS; |
|
660 |
SetLiveRangeAssignedRegister(result, index); |
|
657 | 661 |
fixed_live_ranges_[index] = result; |
658 | 662 |
} |
659 | 663 |
return result; |
... | ... | |
667 | 671 |
result = new(zone()) LiveRange(FixedDoubleLiveRangeID(index), |
668 | 672 |
chunk()->zone()); |
669 | 673 |
ASSERT(result->IsFixed()); |
670 |
SetLiveRangeAssignedRegister(result, index, DOUBLE_REGISTERS); |
|
674 |
result->kind_ = DOUBLE_REGISTERS; |
|
675 |
SetLiveRangeAssignedRegister(result, index); |
|
671 | 676 |
fixed_double_live_ranges_[index] = result; |
672 | 677 |
} |
673 | 678 |
return result; |
... | ... | |
1375 | 1380 |
} |
1376 | 1381 |
#endif |
1377 | 1382 |
} |
1383 |
|
|
1384 |
for (int i = 0; i < live_ranges_.length(); ++i) { |
|
1385 |
if (live_ranges_[i] != NULL) { |
|
1386 |
live_ranges_[i]->kind_ = RequiredRegisterKind(live_ranges_[i]->id()); |
|
1387 |
} |
|
1388 |
} |
|
1378 | 1389 |
} |
1379 | 1390 |
|
1380 | 1391 |
|
... | ... | |
1481 | 1492 |
void LAllocator::AllocateGeneralRegisters() { |
1482 | 1493 |
LAllocatorPhase phase("L_Allocate general registers", this); |
1483 | 1494 |
num_registers_ = Register::NumAllocatableRegisters(); |
1495 |
mode_ = GENERAL_REGISTERS; |
|
1484 | 1496 |
AllocateRegisters(); |
1485 | 1497 |
} |
1486 | 1498 |
|
... | ... | |
1498 | 1510 |
|
1499 | 1511 |
for (int i = 0; i < live_ranges_.length(); ++i) { |
1500 | 1512 |
if (live_ranges_[i] != NULL) { |
1501 |
if (RequiredRegisterKind(live_ranges_[i]->id()) == mode_) {
|
|
1513 |
if (live_ranges_[i]->Kind() == mode_) {
|
|
1502 | 1514 |
AddToUnhandledUnsorted(live_ranges_[i]); |
1503 | 1515 |
} |
1504 | 1516 |
} |
... | ... | |
1518 | 1530 |
} |
1519 | 1531 |
} |
1520 | 1532 |
} else { |
1533 |
ASSERT(mode_ == GENERAL_REGISTERS); |
|
1521 | 1534 |
for (int i = 0; i < fixed_live_ranges_.length(); ++i) { |
1522 | 1535 |
LiveRange* current = fixed_live_ranges_.at(i); |
1523 | 1536 |
if (current != NULL) { |
... | ... | |
1812 | 1825 |
TraceAlloc("Assigning preferred reg %s to live range %d\n", |
1813 | 1826 |
RegisterName(register_index), |
1814 | 1827 |
current->id()); |
1815 |
SetLiveRangeAssignedRegister(current, register_index, mode_);
|
|
1828 |
SetLiveRangeAssignedRegister(current, register_index); |
|
1816 | 1829 |
return true; |
1817 | 1830 |
} |
1818 | 1831 |
} |
... | ... | |
1847 | 1860 |
TraceAlloc("Assigning free reg %s to live range %d\n", |
1848 | 1861 |
RegisterName(reg), |
1849 | 1862 |
current->id()); |
1850 |
SetLiveRangeAssignedRegister(current, reg, mode_);
|
|
1863 |
SetLiveRangeAssignedRegister(current, reg); |
|
1851 | 1864 |
|
1852 | 1865 |
return true; |
1853 | 1866 |
} |
... | ... | |
1932 | 1945 |
TraceAlloc("Assigning blocked reg %s to live range %d\n", |
1933 | 1946 |
RegisterName(reg), |
1934 | 1947 |
current->id()); |
1935 |
SetLiveRangeAssignedRegister(current, reg, mode_);
|
|
1948 |
SetLiveRangeAssignedRegister(current, reg); |
|
1936 | 1949 |
|
1937 | 1950 |
// This register was not free. Thus we need to find and spill |
1938 | 1951 |
// parts of active and inactive live regions that use the same register |
... | ... | |
2149 | 2162 |
|
2150 | 2163 |
if (!first->HasAllocatedSpillOperand()) { |
2151 | 2164 |
LOperand* op = TryReuseSpillSlot(range); |
2152 |
if (op == NULL) op = chunk_->GetNextSpillSlot(mode_ == DOUBLE_REGISTERS);
|
|
2165 |
if (op == NULL) op = chunk_->GetNextSpillSlot(range->Kind());
|
|
2153 | 2166 |
first->SetSpillOperand(op); |
2154 | 2167 |
} |
2155 | 2168 |
range->MakeSpilled(chunk()->zone()); |
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