CSE2410 Fall 2014 Bounce

// Copyright (c) 1994-2006 Sun Microsystems Inc.

// All Rights Reserved.

//

// Redistribution and use in source and binary forms, with or without

// modification, are permitted provided that the following conditions

// are met:

//

// - Redistributions of source code must retain the above copyright notice,

// this list of conditions and the following disclaimer.

//

// - Redistribution in binary form must reproduce the above copyright

// notice, this list of conditions and the following disclaimer in the

// documentation and/or other materials provided with the

// distribution.

//

// - Neither the name of Sun Microsystems or the names of contributors may

// be used to endorse or promote products derived from this software without

// specific prior written permission.

//

// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS

// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,

// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)

// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,

// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED

// OF THE POSSIBILITY OF SUCH DAMAGE.

// The original source code covered by the above license above has been

// modified significantly by Google Inc.

// Copyright 2012 the V8 project authors. All rights reserved.

#include "v8.h"

#if V8_TARGET_ARCH_ARM

#include "arm/assembler-arm-inl.h"

#include "macro-assembler.h"

#include "serialize.h"

namespace v8 {

namespace internal {

#ifdef DEBUG

bool CpuFeatures::initialized_ = false;

#endif

unsigned CpuFeatures::supported_ = 0;

unsigned CpuFeatures::found_by_runtime_probing_only_ = 0;

unsigned CpuFeatures::cross_compile_ = 0;

unsigned CpuFeatures::cache_line_size_ = 64;

ExternalReference ExternalReference::cpu_features() {

  ASSERT(CpuFeatures::initialized_);

  return ExternalReference(&CpuFeatures::supported_);

}

// Get the CPU features enabled by the build. For cross compilation the

// preprocessor symbols CAN_USE_ARMV7_INSTRUCTIONS and CAN_USE_VFP3_INSTRUCTIONS

// can be defined to enable ARMv7 and VFPv3 instructions when building the

// snapshot.

static unsigned CpuFeaturesImpliedByCompiler() {

  unsigned answer = 0;

#ifdef CAN_USE_ARMV7_INSTRUCTIONS

  if (FLAG_enable_armv7) {

    answer |= 1u << ARMv7;

  }

#endif  // CAN_USE_ARMV7_INSTRUCTIONS

#ifdef CAN_USE_VFP3_INSTRUCTIONS

  if (FLAG_enable_vfp3) {

    answer |= 1u << VFP3 | 1u << ARMv7;

  }

#endif  // CAN_USE_VFP3_INSTRUCTIONS

#ifdef CAN_USE_VFP32DREGS

  if (FLAG_enable_32dregs) {

    answer |= 1u << VFP32DREGS;

  }

#endif  // CAN_USE_VFP32DREGS

  if ((answer & (1u << ARMv7)) && FLAG_enable_unaligned_accesses) {

    answer |= 1u << UNALIGNED_ACCESSES;

  }

  return answer;

}

const char* DwVfpRegister::AllocationIndexToString(int index) {

  ASSERT(index >= 0 && index < NumAllocatableRegisters());

  ASSERT(kScratchDoubleReg.code() - kDoubleRegZero.code() ==

         kNumReservedRegisters - 1);

  if (index >= kDoubleRegZero.code())

    index += kNumReservedRegisters;

  return VFPRegisters::Name(index, true);

}

void CpuFeatures::Probe() {

  uint64_t standard_features = static_cast<unsigned>(

      OS::CpuFeaturesImpliedByPlatform()) | CpuFeaturesImpliedByCompiler();

  ASSERT(supported_ == 0 || supported_ == standard_features);

#ifdef DEBUG

  initialized_ = true;

#endif

  // Get the features implied by the OS and the compiler settings. This is the

  // minimal set of features which is also alowed for generated code in the

  // snapshot.

  supported_ |= standard_features;

  if (Serializer::enabled()) {

    // No probing for features if we might serialize (generate snapshot).

    printf("   ");

    PrintFeatures();

    return;

  }

#ifndef __arm__

  // For the simulator=arm build, use VFP when FLAG_enable_vfp3 is

  // enabled. VFPv3 implies ARMv7, see ARM DDI 0406B, page A1-6.

  if (FLAG_enable_vfp3) {

    supported_ |=

        static_cast<uint64_t>(1) << VFP3 |

        static_cast<uint64_t>(1) << ARMv7;

  }

  if (FLAG_enable_neon) {

    supported_ |= 1u << NEON;

  }

  // For the simulator=arm build, use ARMv7 when FLAG_enable_armv7 is enabled

  if (FLAG_enable_armv7) {

    supported_ |= static_cast<uint64_t>(1) << ARMv7;

  }

  if (FLAG_enable_sudiv) {

    supported_ |= static_cast<uint64_t>(1) << SUDIV;

  }

  if (FLAG_enable_movw_movt) {

    supported_ |= static_cast<uint64_t>(1) << MOVW_MOVT_IMMEDIATE_LOADS;

  }

  if (FLAG_enable_32dregs) {

    supported_ |= static_cast<uint64_t>(1) << VFP32DREGS;

  }

  if (FLAG_enable_unaligned_accesses) {

    supported_ |= static_cast<uint64_t>(1) << UNALIGNED_ACCESSES;

  }

#else  // __arm__

  // Probe for additional features not already known to be available.

  CPU cpu;

  if (!IsSupported(VFP3) && FLAG_enable_vfp3 && cpu.has_vfp3()) {

    // This implementation also sets the VFP flags if runtime

    // detection of VFP returns true. VFPv3 implies ARMv7, see ARM DDI

    // 0406B, page A1-6.

    found_by_runtime_probing_only_ |=

        static_cast<uint64_t>(1) << VFP3 |

        static_cast<uint64_t>(1) << ARMv7;

  }

  if (!IsSupported(NEON) && FLAG_enable_neon && cpu.has_neon()) {

    found_by_runtime_probing_only_ |= 1u << NEON;

  }

  if (!IsSupported(ARMv7) && FLAG_enable_armv7 && cpu.architecture() >= 7) {

    found_by_runtime_probing_only_ |= static_cast<uint64_t>(1) << ARMv7;

  }

  if (!IsSupported(SUDIV) && FLAG_enable_sudiv && cpu.has_idiva()) {

    found_by_runtime_probing_only_ |= static_cast<uint64_t>(1) << SUDIV;

  }

  if (!IsSupported(UNALIGNED_ACCESSES) && FLAG_enable_unaligned_accesses

      && cpu.architecture() >= 7) {

    found_by_runtime_probing_only_ |=

        static_cast<uint64_t>(1) << UNALIGNED_ACCESSES;

  }

  // Use movw/movt for QUALCOMM ARMv7 cores.

  if (cpu.implementer() == CPU::QUALCOMM &&

      cpu.architecture() >= 7 &&

      FLAG_enable_movw_movt) {

    found_by_runtime_probing_only_ |=

        static_cast<uint64_t>(1) << MOVW_MOVT_IMMEDIATE_LOADS;

  }

  // ARM Cortex-A9 and Cortex-A5 have 32 byte cachelines.

  if (cpu.implementer() == CPU::ARM &&

      (cpu.part() == CPU::ARM_CORTEX_A5 ||

       cpu.part() == CPU::ARM_CORTEX_A9)) {

    cache_line_size_ = 32;

  }

  if (!IsSupported(VFP32DREGS) && FLAG_enable_32dregs && cpu.has_vfp3_d32()) {

    found_by_runtime_probing_only_ |= static_cast<uint64_t>(1) << VFP32DREGS;

  }

  supported_ |= found_by_runtime_probing_only_;

#endif

  // Assert that VFP3 implies ARMv7.

  ASSERT(!IsSupported(VFP3) || IsSupported(ARMv7));

}

void CpuFeatures::PrintTarget() {

  const char* arm_arch = NULL;

  const char* arm_test = "";

  const char* arm_fpu = "";

  const char* arm_thumb = "";

  const char* arm_float_abi = NULL;

#if defined CAN_USE_ARMV7_INSTRUCTIONS

  arm_arch = "arm v7";

#else

  arm_arch = "arm v6";

#endif

#ifdef __arm__

# ifdef ARM_TEST

  arm_test = " test";

# endif

# if defined __ARM_NEON__

  arm_fpu = " neon";

# elif defined CAN_USE_VFP3_INSTRUCTIONS

  arm_fpu = " vfp3";

# else

  arm_fpu = " vfp2";

# endif

# if (defined __thumb__) || (defined __thumb2__)

  arm_thumb = " thumb";

# endif

  arm_float_abi = OS::ArmUsingHardFloat() ? "hard" : "softfp";

#else  // __arm__

  arm_test = " simulator";

# if defined CAN_USE_VFP3_INSTRUCTIONS

#  if defined CAN_USE_VFP32DREGS

  arm_fpu = " vfp3";

#  else

  arm_fpu = " vfp3-d16";

#  endif

# else

  arm_fpu = " vfp2";

# endif

# if USE_EABI_HARDFLOAT == 1

  arm_float_abi = "hard";

# else

  arm_float_abi = "softfp";

# endif

#endif  // __arm__

  printf("target%s %s%s%s %s\n",

         arm_test, arm_arch, arm_fpu, arm_thumb, arm_float_abi);

}

void CpuFeatures::PrintFeatures() {

  printf(

    "ARMv7=%d VFP3=%d VFP32DREGS=%d NEON=%d SUDIV=%d UNALIGNED_ACCESSES=%d "

    "MOVW_MOVT_IMMEDIATE_LOADS=%d",

    CpuFeatures::IsSupported(ARMv7),

    CpuFeatures::IsSupported(VFP3),

    CpuFeatures::IsSupported(VFP32DREGS),

    CpuFeatures::IsSupported(NEON),

    CpuFeatures::IsSupported(SUDIV),

    CpuFeatures::IsSupported(UNALIGNED_ACCESSES),

    CpuFeatures::IsSupported(MOVW_MOVT_IMMEDIATE_LOADS));

#ifdef __arm__

  bool eabi_hardfloat = OS::ArmUsingHardFloat();

#elif USE_EABI_HARDFLOAT

  bool eabi_hardfloat = true;

#else

  bool eabi_hardfloat = false;

#endif

    printf(" USE_EABI_HARDFLOAT=%d\n", eabi_hardfloat);

}

// -----------------------------------------------------------------------------

// Implementation of RelocInfo

const int RelocInfo::kApplyMask = 0;

bool RelocInfo::IsCodedSpecially() {

  // The deserializer needs to know whether a pointer is specially coded.  Being

  // specially coded on ARM means that it is a movw/movt instruction.  We don't

  // generate those yet.

  return false;

}

void RelocInfo::PatchCode(byte* instructions, int instruction_count) {

  // Patch the code at the current address with the supplied instructions.

  Instr* pc = reinterpret_cast<Instr*>(pc_);

  Instr* instr = reinterpret_cast<Instr*>(instructions);

  for (int i = 0; i < instruction_count; i++) {

    *(pc + i) = *(instr + i);

  }

  // Indicate that code has changed.

  CPU::FlushICache(pc_, instruction_count * Assembler::kInstrSize);

}

// Patch the code at the current PC with a call to the target address.

// Additional guard instructions can be added if required.

void RelocInfo::PatchCodeWithCall(Address target, int guard_bytes) {

  // Patch the code at the current address with a call to the target.

  UNIMPLEMENTED();

}

// -----------------------------------------------------------------------------

// Implementation of Operand and MemOperand

// See assembler-arm-inl.h for inlined constructors

Operand::Operand(Handle<Object> handle) {

  AllowDeferredHandleDereference using_raw_address;

  rm_ = no_reg;

  // Verify all Objects referred by code are NOT in new space.

  Object* obj = *handle;

  if (obj->IsHeapObject()) {

    ASSERT(!HeapObject::cast(obj)->GetHeap()->InNewSpace(obj));

    imm32_ = reinterpret_cast<intptr_t>(handle.location());

    rmode_ = RelocInfo::EMBEDDED_OBJECT;

  } else {

    // no relocation needed

    imm32_ = reinterpret_cast<intptr_t>(obj);

    rmode_ = RelocInfo::NONE32;

  }

}

Operand::Operand(Register rm, ShiftOp shift_op, int shift_imm) {

  ASSERT(is_uint5(shift_imm));

  ASSERT(shift_op != ROR || shift_imm != 0);  // use RRX if you mean it

  rm_ = rm;

  rs_ = no_reg;

  shift_op_ = shift_op;

  shift_imm_ = shift_imm & 31;

  if (shift_op == RRX) {

    // encoded as ROR with shift_imm == 0

    ASSERT(shift_imm == 0);

    shift_op_ = ROR;

    shift_imm_ = 0;

  }

}

Operand::Operand(Register rm, ShiftOp shift_op, Register rs) {

  ASSERT(shift_op != RRX);

  rm_ = rm;

  rs_ = no_reg;

  shift_op_ = shift_op;

  rs_ = rs;

}

MemOperand::MemOperand(Register rn, int32_t offset, AddrMode am) {

  rn_ = rn;

  rm_ = no_reg;

  offset_ = offset;

  am_ = am;

}

MemOperand::MemOperand(Register rn, Register rm, AddrMode am) {

  rn_ = rn;

  rm_ = rm;

  shift_op_ = LSL;

  shift_imm_ = 0;

  am_ = am;

}

MemOperand::MemOperand(Register rn, Register rm,

                       ShiftOp shift_op, int shift_imm, AddrMode am) {

  ASSERT(is_uint5(shift_imm));

  rn_ = rn;

  rm_ = rm;

  shift_op_ = shift_op;

  shift_imm_ = shift_imm & 31;

  am_ = am;

}

NeonMemOperand::NeonMemOperand(Register rn, AddrMode am, int align) {

  ASSERT((am == Offset) || (am == PostIndex));

  rn_ = rn;

  rm_ = (am == Offset) ? pc : sp;

  SetAlignment(align);

}

NeonMemOperand::NeonMemOperand(Register rn, Register rm, int align) {

  rn_ = rn;

  rm_ = rm;

  SetAlignment(align);

}

void NeonMemOperand::SetAlignment(int align) {

  switch (align) {

    case 0:

      align_ = 0;

      break;

    case 64:

      align_ = 1;

      break;

    case 128:

      align_ = 2;

      break;

    case 256:

      align_ = 3;

      break;

    default:

      UNREACHABLE();

      align_ = 0;

      break;

  }

}

NeonListOperand::NeonListOperand(DoubleRegister base, int registers_count) {

  base_ = base;

  switch (registers_count) {

    case 1:

      type_ = nlt_1;

      break;

    case 2:

      type_ = nlt_2;

      break;

    case 3:

      type_ = nlt_3;

      break;

    case 4:

      type_ = nlt_4;

      break;

    default:

      UNREACHABLE();

      type_ = nlt_1;

      break;

  }

}

// -----------------------------------------------------------------------------

// Specific instructions, constants, and masks.

// add(sp, sp, 4) instruction (aka Pop())

const Instr kPopInstruction =

    al | PostIndex | 4 | LeaveCC | I | kRegister_sp_Code * B16 |

        kRegister_sp_Code * B12;

// str(r, MemOperand(sp, 4, NegPreIndex), al) instruction (aka push(r))

// register r is not encoded.

const Instr kPushRegPattern =

    al | B26 | 4 | NegPreIndex | kRegister_sp_Code * B16;

// ldr(r, MemOperand(sp, 4, PostIndex), al) instruction (aka pop(r))

// register r is not encoded.

const Instr kPopRegPattern =

    al | B26 | L | 4 | PostIndex | kRegister_sp_Code * B16;

// mov lr, pc

const Instr kMovLrPc = al | MOV | kRegister_pc_Code | kRegister_lr_Code * B12;

// ldr rd, [pc, #offset]

const Instr kLdrPCMask = 15 * B24 | 7 * B20 | 15 * B16;

const Instr kLdrPCPattern = 5 * B24 | L | kRegister_pc_Code * B16;

// vldr dd, [pc, #offset]

const Instr kVldrDPCMask = 15 * B24 | 3 * B20 | 15 * B16 | 15 * B8;

const Instr kVldrDPCPattern = 13 * B24 | L | kRegister_pc_Code * B16 | 11 * B8;

// blxcc rm

const Instr kBlxRegMask =

    15 * B24 | 15 * B20 | 15 * B16 | 15 * B12 | 15 * B8 | 15 * B4;

const Instr kBlxRegPattern =

    B24 | B21 | 15 * B16 | 15 * B12 | 15 * B8 | BLX;

const Instr kBlxIp = al | kBlxRegPattern | ip.code();

const Instr kMovMvnMask = 0x6d * B21 | 0xf * B16;

const Instr kMovMvnPattern = 0xd * B21;

const Instr kMovMvnFlip = B22;

const Instr kMovLeaveCCMask = 0xdff * B16;

const Instr kMovLeaveCCPattern = 0x1a0 * B16;

const Instr kMovwMask = 0xff * B20;

const Instr kMovwPattern = 0x30 * B20;

const Instr kMovwLeaveCCFlip = 0x5 * B21;

const Instr kCmpCmnMask = 0xdd * B20 | 0xf * B12;

const Instr kCmpCmnPattern = 0x15 * B20;

const Instr kCmpCmnFlip = B21;

const Instr kAddSubFlip = 0x6 * B21;

const Instr kAndBicFlip = 0xe * B21;

// A mask for the Rd register for push, pop, ldr, str instructions.

const Instr kLdrRegFpOffsetPattern =

    al | B26 | L | Offset | kRegister_fp_Code * B16;

const Instr kStrRegFpOffsetPattern =

    al | B26 | Offset | kRegister_fp_Code * B16;

const Instr kLdrRegFpNegOffsetPattern =

    al | B26 | L | NegOffset | kRegister_fp_Code * B16;

const Instr kStrRegFpNegOffsetPattern =

    al | B26 | NegOffset | kRegister_fp_Code * B16;

const Instr kLdrStrInstrTypeMask = 0xffff0000;

const Instr kLdrStrInstrArgumentMask = 0x0000ffff;

const Instr kLdrStrOffsetMask = 0x00000fff;

Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size)

    : AssemblerBase(isolate, buffer, buffer_size),

      recorded_ast_id_(TypeFeedbackId::None()),

      positions_recorder_(this) {

  reloc_info_writer.Reposition(buffer_ + buffer_size_, pc_);

  num_pending_reloc_info_ = 0;

  num_pending_64_bit_reloc_info_ = 0;

  next_buffer_check_ = 0;

  const_pool_blocked_nesting_ = 0;

  no_const_pool_before_ = 0;

  first_const_pool_use_ = -1;

  last_bound_pos_ = 0;

  ClearRecordedAstId();

}

Assembler::~Assembler() {

  ASSERT(const_pool_blocked_nesting_ == 0);

}

void Assembler::GetCode(CodeDesc* desc) {

  // Emit constant pool if necessary.

  CheckConstPool(true, false);

  ASSERT(num_pending_reloc_info_ == 0);

  ASSERT(num_pending_64_bit_reloc_info_ == 0);

  // Set up code descriptor.

  desc->buffer = buffer_;

  desc->buffer_size = buffer_size_;

  desc->instr_size = pc_offset();

  desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();

}

void Assembler::Align(int m) {

  ASSERT(m >= 4 && IsPowerOf2(m));

  while ((pc_offset() & (m - 1)) != 0) {

    nop();

  }

}

void Assembler::CodeTargetAlign() {

  // Preferred alignment of jump targets on some ARM chips.

  Align(8);

}

Condition Assembler::GetCondition(Instr instr) {

  return Instruction::ConditionField(instr);

}

bool Assembler::IsBranch(Instr instr) {

  return (instr & (B27 | B25)) == (B27 | B25);

}

int Assembler::GetBranchOffset(Instr instr) {

  ASSERT(IsBranch(instr));

  // Take the jump offset in the lower 24 bits, sign extend it and multiply it

  // with 4 to get the offset in bytes.

  return ((instr & kImm24Mask) << 8) >> 6;

}

bool Assembler::IsLdrRegisterImmediate(Instr instr) {

  return (instr & (B27 | B26 | B25 | B22 | B20)) == (B26 | B20);

}

bool Assembler::IsVldrDRegisterImmediate(Instr instr) {

  return (instr & (15 * B24 | 3 * B20 | 15 * B8)) == (13 * B24 | B20 | 11 * B8);

}

int Assembler::GetLdrRegisterImmediateOffset(Instr instr) {

  ASSERT(IsLdrRegisterImmediate(instr));

  bool positive = (instr & B23) == B23;

  int offset = instr & kOff12Mask;  // Zero extended offset.

  return positive ? offset : -offset;

}

int Assembler::GetVldrDRegisterImmediateOffset(Instr instr) {

  ASSERT(IsVldrDRegisterImmediate(instr));

  bool positive = (instr & B23) == B23;

  int offset = instr & kOff8Mask;  // Zero extended offset.

  offset <<= 2;

  return positive ? offset : -offset;

}

Instr Assembler::SetLdrRegisterImmediateOffset(Instr instr, int offset) {

  ASSERT(IsLdrRegisterImmediate(instr));

  bool positive = offset >= 0;

  if (!positive) offset = -offset;

  ASSERT(is_uint12(offset));

  // Set bit indicating whether the offset should be added.

  instr = (instr & ~B23) | (positive ? B23 : 0);

  // Set the actual offset.

  return (instr & ~kOff12Mask) | offset;

}

Instr Assembler::SetVldrDRegisterImmediateOffset(Instr instr, int offset) {

  ASSERT(IsVldrDRegisterImmediate(instr));

  ASSERT((offset & ~3) == offset);  // Must be 64-bit aligned.

  bool positive = offset >= 0;

  if (!positive) offset = -offset;

  ASSERT(is_uint10(offset));

  // Set bit indicating whether the offset should be added.

  instr = (instr & ~B23) | (positive ? B23 : 0);

  // Set the actual offset. Its bottom 2 bits are zero.

  return (instr & ~kOff8Mask) | (offset >> 2);

}

bool Assembler::IsStrRegisterImmediate(Instr instr) {

  return (instr & (B27 | B26 | B25 | B22 | B20)) == B26;

}

Instr Assembler::SetStrRegisterImmediateOffset(Instr instr, int offset) {

  ASSERT(IsStrRegisterImmediate(instr));

  bool positive = offset >= 0;

  if (!positive) offset = -offset;

  ASSERT(is_uint12(offset));

  // Set bit indicating whether the offset should be added.

  instr = (instr & ~B23) | (positive ? B23 : 0);

  // Set the actual offset.

  return (instr & ~kOff12Mask) | offset;

}

bool Assembler::IsAddRegisterImmediate(Instr instr) {

  return (instr & (B27 | B26 | B25 | B24 | B23 | B22 | B21)) == (B25 | B23);

}

Instr Assembler::SetAddRegisterImmediateOffset(Instr instr, int offset) {

  ASSERT(IsAddRegisterImmediate(instr));

  ASSERT(offset >= 0);

  ASSERT(is_uint12(offset));

  // Set the offset.

  return (instr & ~kOff12Mask) | offset;

}

Register Assembler::GetRd(Instr instr) {

  Register reg;

  reg.code_ = Instruction::RdValue(instr);

  return reg;

}

Register Assembler::GetRn(Instr instr) {

  Register reg;

  reg.code_ = Instruction::RnValue(instr);

  return reg;

}

Register Assembler::GetRm(Instr instr) {

  Register reg;

  reg.code_ = Instruction::RmValue(instr);

  return reg;

}

bool Assembler::IsPush(Instr instr) {

  return ((instr & ~kRdMask) == kPushRegPattern);

}

bool Assembler::IsPop(Instr instr) {

  return ((instr & ~kRdMask) == kPopRegPattern);

}

bool Assembler::IsStrRegFpOffset(Instr instr) {

  return ((instr & kLdrStrInstrTypeMask) == kStrRegFpOffsetPattern);

}

bool Assembler::IsLdrRegFpOffset(Instr instr) {

  return ((instr & kLdrStrInstrTypeMask) == kLdrRegFpOffsetPattern);

}

bool Assembler::IsStrRegFpNegOffset(Instr instr) {

  return ((instr & kLdrStrInstrTypeMask) == kStrRegFpNegOffsetPattern);

}

bool Assembler::IsLdrRegFpNegOffset(Instr instr) {

  return ((instr & kLdrStrInstrTypeMask) == kLdrRegFpNegOffsetPattern);

}

bool Assembler::IsLdrPcImmediateOffset(Instr instr) {

  // Check the instruction is indeed a

  // ldr<cond> <Rd>, [pc +/- offset_12].

  return (instr & kLdrPCMask) == kLdrPCPattern;

}

bool Assembler::IsVldrDPcImmediateOffset(Instr instr) {

  // Check the instruction is indeed a

  // vldr<cond> <Dd>, [pc +/- offset_10].

  return (instr & kVldrDPCMask) == kVldrDPCPattern;

}

bool Assembler::IsTstImmediate(Instr instr) {

  return (instr & (B27 | B26 | I | kOpCodeMask | S | kRdMask)) ==

      (I | TST | S);

}

bool Assembler::IsCmpRegister(Instr instr) {

  return (instr & (B27 | B26 | I | kOpCodeMask | S | kRdMask | B4)) ==

      (CMP | S);

}

bool Assembler::IsCmpImmediate(Instr instr) {

  return (instr & (B27 | B26 | I | kOpCodeMask | S | kRdMask)) ==

      (I | CMP | S);

}

Register Assembler::GetCmpImmediateRegister(Instr instr) {

  ASSERT(IsCmpImmediate(instr));

  return GetRn(instr);

}

int Assembler::GetCmpImmediateRawImmediate(Instr instr) {

  ASSERT(IsCmpImmediate(instr));

  return instr & kOff12Mask;

}

// Labels refer to positions in the (to be) generated code.

// There are bound, linked, and unused labels.

//

// Bound labels refer to known positions in the already

// generated code. pos() is the position the label refers to.

//

// Linked labels refer to unknown positions in the code

// to be generated; pos() is the position of the last

// instruction using the label.

//

// The linked labels form a link chain by making the branch offset

// in the instruction steam to point to the previous branch

// instruction using the same label.

//

// The link chain is terminated by a branch offset pointing to the

// same position.

int Assembler::target_at(int pos)  {

  Instr instr = instr_at(pos);

  if (is_uint24(instr)) {

    // Emitted link to a label, not part of a branch.

    return instr;

  }

  ASSERT((instr & 7*B25) == 5*B25);  // b, bl, or blx imm24

  int imm26 = ((instr & kImm24Mask) << 8) >> 6;

  if ((Instruction::ConditionField(instr) == kSpecialCondition) &&

      ((instr & B24) != 0)) {

    // blx uses bit 24 to encode bit 2 of imm26

    imm26 += 2;

  }

  return pos + kPcLoadDelta + imm26;

}

void Assembler::target_at_put(int pos, int target_pos) {

  Instr instr = instr_at(pos);

  if (is_uint24(instr)) {

    ASSERT(target_pos == pos || target_pos >= 0);

    // Emitted link to a label, not part of a branch.

    // Load the position of the label relative to the generated code object

    // pointer in a register.

    // Here are the instructions we need to emit:

    //   For ARMv7: target24 => target16_1:target16_0

    //      movw dst, #target16_0

    //      movt dst, #target16_1

    //   For ARMv6: target24 => target8_2:target8_1:target8_0

    //      mov dst, #target8_0

    //      orr dst, dst, #target8_1 << 8

    //      orr dst, dst, #target8_2 << 16

    // We extract the destination register from the emitted nop instruction.

    Register dst = Register::from_code(

        Instruction::RmValue(instr_at(pos + kInstrSize)));

    ASSERT(IsNop(instr_at(pos + kInstrSize), dst.code()));

    uint32_t target24 = target_pos + (Code::kHeaderSize - kHeapObjectTag);

    ASSERT(is_uint24(target24));

    if (is_uint8(target24)) {

      // If the target fits in a byte then only patch with a mov

      // instruction.

      CodePatcher patcher(reinterpret_cast<byte*>(buffer_ + pos),

                          1,

                          CodePatcher::DONT_FLUSH);

      patcher.masm()->mov(dst, Operand(target24));

    } else {

      uint16_t target16_0 = target24 & kImm16Mask;

      uint16_t target16_1 = target24 >> 16;

      if (CpuFeatures::IsSupported(ARMv7)) {

        // Patch with movw/movt.

        if (target16_1 == 0) {

          CodePatcher patcher(reinterpret_cast<byte*>(buffer_ + pos),

                              1,

                              CodePatcher::DONT_FLUSH);

          patcher.masm()->movw(dst, target16_0);

        } else {

          CodePatcher patcher(reinterpret_cast<byte*>(buffer_ + pos),

                              2,

                              CodePatcher::DONT_FLUSH);

          patcher.masm()->movw(dst, target16_0);

          patcher.masm()->movt(dst, target16_1);

        }

      } else {

        // Patch with a sequence of mov/orr/orr instructions.

        uint8_t target8_0 = target16_0 & kImm8Mask;

        uint8_t target8_1 = target16_0 >> 8;

        uint8_t target8_2 = target16_1 & kImm8Mask;

        if (target8_2 == 0) {

          CodePatcher patcher(reinterpret_cast<byte*>(buffer_ + pos),

                              2,

                              CodePatcher::DONT_FLUSH);

          patcher.masm()->mov(dst, Operand(target8_0));

          patcher.masm()->orr(dst, dst, Operand(target8_1 << 8));

        } else {

          CodePatcher patcher(reinterpret_cast<byte*>(buffer_ + pos),

                              3,

                              CodePatcher::DONT_FLUSH);

          patcher.masm()->mov(dst, Operand(target8_0));

          patcher.masm()->orr(dst, dst, Operand(target8_1 << 8));

          patcher.masm()->orr(dst, dst, Operand(target8_2 << 16));

        }

      }

    }

    return;

  }

  int imm26 = target_pos - (pos + kPcLoadDelta);

  ASSERT((instr & 7*B25) == 5*B25);  // b, bl, or blx imm24

  if (Instruction::ConditionField(instr) == kSpecialCondition) {

    // blx uses bit 24 to encode bit 2 of imm26

    ASSERT((imm26 & 1) == 0);

    instr = (instr & ~(B24 | kImm24Mask)) | ((imm26 & 2) >> 1)*B24;

  } else {

    ASSERT((imm26 & 3) == 0);

    instr &= ~kImm24Mask;

  }

  int imm24 = imm26 >> 2;

  ASSERT(is_int24(imm24));

  instr_at_put(pos, instr | (imm24 & kImm24Mask));

}

void Assembler::print(Label* L) {

  if (L->is_unused()) {

    PrintF("unused label\n");

  } else if (L->is_bound()) {

    PrintF("bound label to %d\n", L->pos());

  } else if (L->is_linked()) {

    Label l = *L;

    PrintF("unbound label");

    while (l.is_linked()) {

      PrintF("@ %d ", l.pos());

      Instr instr = instr_at(l.pos());

      if ((instr & ~kImm24Mask) == 0) {

        PrintF("value\n");

      } else {

        ASSERT((instr & 7*B25) == 5*B25);  // b, bl, or blx

        Condition cond = Instruction::ConditionField(instr);

        const char* b;

        const char* c;

        if (cond == kSpecialCondition) {

          b = "blx";

          c = "";

        } else {

          if ((instr & B24) != 0)

            b = "bl";

          else

            b = "b";

          switch (cond) {

            case eq: c = "eq"; break;

            case ne: c = "ne"; break;

            case hs: c = "hs"; break;

            case lo: c = "lo"; break;

            case mi: c = "mi"; break;

            case pl: c = "pl"; break;

            case vs: c = "vs"; break;

            case vc: c = "vc"; break;

            case hi: c = "hi"; break;

            case ls: c = "ls"; break;

            case ge: c = "ge"; break;

            case lt: c = "lt"; break;

            case gt: c = "gt"; break;

            case le: c = "le"; break;

            case al: c = ""; break;

            default:

              c = "";

              UNREACHABLE();

          }

        }

        PrintF("%s%s\n", b, c);

      }

      next(&l);

    }

  } else {

    PrintF("label in inconsistent state (pos = %d)\n", L->pos_);

  }

}

void Assembler::bind_to(Label* L, int pos) {

  ASSERT(0 <= pos && pos <= pc_offset());  // must have a valid binding position

  while (L->is_linked()) {

    int fixup_pos = L->pos();

    next(L);  // call next before overwriting link with target at fixup_pos

    target_at_put(fixup_pos, pos);

  }

  L->bind_to(pos);

  // Keep track of the last bound label so we don't eliminate any instructions

  // before a bound label.

  if (pos > last_bound_pos_)

    last_bound_pos_ = pos;

}

void Assembler::bind(Label* L) {

  ASSERT(!L->is_bound());  // label can only be bound once

  bind_to(L, pc_offset());

}

void Assembler::next(Label* L) {

  ASSERT(L->is_linked());

  int link = target_at(L->pos());

  if (link == L->pos()) {

    // Branch target points to the same instuction. This is the end of the link

    // chain.

    L->Unuse();

  } else {

    ASSERT(link >= 0);

    L->link_to(link);

  }

}

// Low-level code emission routines depending on the addressing mode.

// If this returns true then you have to use the rotate_imm and immed_8

// that it returns, because it may have already changed the instruction

// to match them!

static bool fits_shifter(uint32_t imm32,

                         uint32_t* rotate_imm,

                         uint32_t* immed_8,

                         Instr* instr) {

  // imm32 must be unsigned.

  for (int rot = 0; rot < 16; rot++) {

    uint32_t imm8 = (imm32 << 2*rot) | (imm32 >> (32 - 2*rot));

    if ((imm8 <= 0xff)) {

      *rotate_imm = rot;

      *immed_8 = imm8;

      return true;

    }

  }

  // If the opcode is one with a complementary version and the complementary

  // immediate fits, change the opcode.

  if (instr != NULL) {

    if ((*instr & kMovMvnMask) == kMovMvnPattern) {

      if (fits_shifter(~imm32, rotate_imm, immed_8, NULL)) {

        *instr ^= kMovMvnFlip;

        return true;

      } else if ((*instr & kMovLeaveCCMask) == kMovLeaveCCPattern) {

        if (CpuFeatures::IsSupported(ARMv7)) {

          if (imm32 < 0x10000) {

            *instr ^= kMovwLeaveCCFlip;

            *instr |= EncodeMovwImmediate(imm32);

            *rotate_imm = *immed_8 = 0;  // Not used for movw.

            return true;

          }

        }

      }

    } else if ((*instr & kCmpCmnMask) == kCmpCmnPattern) {

      if (fits_shifter(-static_cast<int>(imm32), rotate_imm, immed_8, NULL)) {

        *instr ^= kCmpCmnFlip;

        return true;

      }

    } else {

      Instr alu_insn = (*instr & kALUMask);

      if (alu_insn == ADD ||

          alu_insn == SUB) {

        if (fits_shifter(-static_cast<int>(imm32), rotate_imm, immed_8, NULL)) {

          *instr ^= kAddSubFlip;

          return true;

        }

      } else if (alu_insn == AND ||

                 alu_insn == BIC) {

        if (fits_shifter(~imm32, rotate_imm, immed_8, NULL)) {

          *instr ^= kAndBicFlip;

          return true;

        }

      }

    }

  }

  return false;

}

// We have to use the temporary register for things that can be relocated even

// if they can be encoded in the ARM's 12 bits of immediate-offset instruction

// space.  There is no guarantee that the relocated location can be similarly

// encoded.

bool Operand::must_output_reloc_info(const Assembler* assembler) const {

  if (rmode_ == RelocInfo::EXTERNAL_REFERENCE) {

#ifdef DEBUG

    if (!Serializer::enabled()) {

      Serializer::TooLateToEnableNow();

    }

#endif  // def DEBUG

    if (assembler != NULL && assembler->predictable_code_size()) return true;

    return Serializer::enabled();

  } else if (RelocInfo::IsNone(rmode_)) {

    return false;

  }

  return true;

}

static bool use_movw_movt(const Operand& x, const Assembler* assembler) {

  if (Assembler::use_immediate_embedded_pointer_loads(assembler)) {

    return true;

  }

  if (x.must_output_reloc_info(assembler)) {

    return false;

  }

  return CpuFeatures::IsSupported(ARMv7);

}

bool Operand::is_single_instruction(const Assembler* assembler,

                                    Instr instr) const {

  if (rm_.is_valid()) return true;

  uint32_t dummy1, dummy2;

  if (must_output_reloc_info(assembler) ||

      !fits_shifter(imm32_, &dummy1, &dummy2, &instr)) {

    // The immediate operand cannot be encoded as a shifter operand, or use of

    // constant pool is required. For a mov instruction not setting the

    // condition code additional instruction conventions can be used.

    if ((instr & ~kCondMask) == 13*B21) {  // mov, S not set

      return !use_movw_movt(*this, assembler);

    } else {

      // If this is not a mov or mvn instruction there will always an additional

      // instructions - either mov or ldr. The mov might actually be two

      // instructions mov or movw followed by movt so including the actual

      // instruction two or three instructions will be generated.

      return false;

    }

  } else {

    // No use of constant pool and the immediate operand can be encoded as a

    // shifter operand.

    return true;

  }

}

void Assembler::move_32_bit_immediate(Condition cond,

                                      Register rd,

                                      SBit s,

                                      const Operand& x) {

  if (rd.code() != pc.code() && s == LeaveCC) {

    if (use_movw_movt(x, this)) {

      if (x.must_output_reloc_info(this)) {

        RecordRelocInfo(x.rmode_, x.imm32_, DONT_USE_CONSTANT_POOL);

        // Make sure the movw/movt doesn't get separated.

        BlockConstPoolFor(2);

      }

      emit(cond | 0x30*B20 | rd.code()*B12 |

           EncodeMovwImmediate(x.imm32_ & 0xffff));

      movt(rd, static_cast<uint32_t>(x.imm32_) >> 16, cond);

      return;

    }

  }

  RecordRelocInfo(x.rmode_, x.imm32_, USE_CONSTANT_POOL);

  ldr(rd, MemOperand(pc, 0), cond);

}

void Assembler::addrmod1(Instr instr,

                         Register rn,

                         Register rd,

                         const Operand& x) {

  CheckBuffer();

  ASSERT((instr & ~(kCondMask | kOpCodeMask | S)) == 0);

  if (!x.rm_.is_valid()) {

    // Immediate.

    uint32_t rotate_imm;

    uint32_t immed_8;

    if (x.must_output_reloc_info(this) ||

        !fits_shifter(x.imm32_, &rotate_imm, &immed_8, &instr)) {

      // The immediate operand cannot be encoded as a shifter operand, so load

      // it first to register ip and change the original instruction to use ip.

      // However, if the original instruction is a 'mov rd, x' (not setting the

      // condition code), then replace it with a 'ldr rd, [pc]'.

      CHECK(!rn.is(ip));  // rn should never be ip, or will be trashed

      Condition cond = Instruction::ConditionField(instr);

      if ((instr & ~kCondMask) == 13*B21) {  // mov, S not set

        move_32_bit_immediate(cond, rd, LeaveCC, x);

      } else {

        if ((instr & kMovMvnMask) == kMovMvnPattern) {

          // Moves need to use a constant pool entry.

          RecordRelocInfo(x.rmode_, x.imm32_, USE_CONSTANT_POOL);

          ldr(ip, MemOperand(pc, 0), cond);

        } else if (x.must_output_reloc_info(this)) {

          // Otherwise, use most efficient form of fetching from constant pool.

          move_32_bit_immediate(cond, ip, LeaveCC, x);

        } else {

          // If this is not a mov or mvn instruction we may still be able to

          // avoid a constant pool entry by using mvn or movw.

          mov(ip, x, LeaveCC, cond);

        }

        addrmod1(instr, rn, rd, Operand(ip));

      }

      return;

    }

    instr |= I | rotate_imm*B8 | immed_8;

  } else if (!x.rs_.is_valid()) {

    // Immediate shift.

    instr |= x.shift_imm_*B7 | x.shift_op_ | x.rm_.code();

  } else {

    // Register shift.

    ASSERT(!rn.is(pc) && !rd.is(pc) && !x.rm_.is(pc) && !x.rs_.is(pc));

    instr |= x.rs_.code()*B8 | x.shift_op_ | B4 | x.rm_.code();

  }

  emit(instr | rn.code()*B16 | rd.code()*B12);

  if (rn.is(pc) || x.rm_.is(pc)) {

    // Block constant pool emission for one instruction after reading pc.

    BlockConstPoolFor(1);

  }

}

void Assembler::addrmod2(Instr instr, Register rd, const MemOperand& x) {

  ASSERT((instr & ~(kCondMask | B | L)) == B26);

  int am = x.am_;

  if (!x.rm_.is_valid()) {

    // Immediate offset.

    int offset_12 = x.offset_;

    if (offset_12 < 0) {

      offset_12 = -offset_12;

      am ^= U;

    }

    if (!is_uint12(offset_12)) {

      // Immediate offset cannot be encoded, load it first to register ip

      // rn (and rd in a load) should never be ip, or will be trashed.

      ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip)));

      mov(ip, Operand(x.offset_), LeaveCC, Instruction::ConditionField(instr));

      addrmod2(instr, rd, MemOperand(x.rn_, ip, x.am_));

      return;

    }

    ASSERT(offset_12 >= 0);  // no masking needed

    instr |= offset_12;

  } else {

    // Register offset (shift_imm_ and shift_op_ are 0) or scaled

    // register offset the constructors make sure than both shift_imm_

    // and shift_op_ are initialized.

    ASSERT(!x.rm_.is(pc));

    instr |= B25 | x.shift_imm_*B7 | x.shift_op_ | x.rm_.code();

  }

  ASSERT((am & (P|W)) == P || !x.rn_.is(pc));  // no pc base with writeback

  emit(instr | am | x.rn_.code()*B16 | rd.code()*B12);

}

void Assembler::addrmod3(Instr instr, Register rd, const MemOperand& x) {

  ASSERT((instr & ~(kCondMask | L | S6 | H)) == (B4 | B7));

  ASSERT(x.rn_.is_valid());

  int am = x.am_;

  if (!x.rm_.is_valid()) {

    // Immediate offset.

    int offset_8 = x.offset_;

    if (offset_8 < 0) {

      offset_8 = -offset_8;

      am ^= U;

    }

    if (!is_uint8(offset_8)) {

      // Immediate offset cannot be encoded, load it first to register ip

      // rn (and rd in a load) should never be ip, or will be trashed.

      ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip)));

      mov(ip, Operand(x.offset_), LeaveCC, Instruction::ConditionField(instr));

      addrmod3(instr, rd, MemOperand(x.rn_, ip, x.am_));

      return;

    }

    ASSERT(offset_8 >= 0);  // no masking needed

    instr |= B | (offset_8 >> 4)*B8 | (offset_8 & 0xf);

  } else if (x.shift_imm_ != 0) {

    // Scaled register offset not supported, load index first

    // rn (and rd in a load) should never be ip, or will be trashed.

    ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip)));

    mov(ip, Operand(x.rm_, x.shift_op_, x.shift_imm_), LeaveCC,

        Instruction::ConditionField(instr));

    addrmod3(instr, rd, MemOperand(x.rn_, ip, x.am_));

    return;

  } else {

    // Register offset.

    ASSERT((am & (P|W)) == P || !x.rm_.is(pc));  // no pc index with writeback

    instr |= x.rm_.code();

  }

  ASSERT((am & (P|W)) == P || !x.rn_.is(pc));  // no pc base with writeback

  emit(instr | am | x.rn_.code()*B16 | rd.code()*B12);

}

void Assembler::addrmod4(Instr instr, Register rn, RegList rl) {

  ASSERT((instr & ~(kCondMask | P | U | W | L)) == B27);

  ASSERT(rl != 0);

  ASSERT(!rn.is(pc));

  emit(instr | rn.code()*B16 | rl);

}

void Assembler::addrmod5(Instr instr, CRegister crd, const MemOperand& x) {

  // Unindexed addressing is not encoded by this function.

  ASSERT_EQ((B27 | B26),

            (instr & ~(kCondMask | kCoprocessorMask | P | U | N | W | L)));

  ASSERT(x.rn_.is_valid() && !x.rm_.is_valid());

  int am = x.am_;

  int offset_8 = x.offset_;

  ASSERT((offset_8 & 3) == 0);  // offset must be an aligned word offset

  offset_8 >>= 2;

  if (offset_8 < 0) {

    offset_8 = -offset_8;

    am ^= U;

  }

  ASSERT(is_uint8(offset_8));  // unsigned word offset must fit in a byte

  ASSERT((am & (P|W)) == P || !x.rn_.is(pc));  // no pc base with writeback

  // Post-indexed addressing requires W == 1; different than in addrmod2/3.

  if ((am & P) == 0)

    am |= W;

  ASSERT(offset_8 >= 0);  // no masking needed

  emit(instr | am | x.rn_.code()*B16 | crd.code()*B12 | offset_8);

}

int Assembler::branch_offset(Label* L, bool jump_elimination_allowed) {

  int target_pos;

  if (L->is_bound()) {

    target_pos = L->pos();

  } else {

    if (L->is_linked()) {

      // Point to previous instruction that uses the link.

      target_pos = L->pos();

    } else {

      // First entry of the link chain points to itself.

      target_pos = pc_offset();

    }

    L->link_to(pc_offset());

  }

  // Block the emission of the constant pool, since the branch instruction must

  // be emitted at the pc offset recorded by the label.

  BlockConstPoolFor(1);

  return target_pos - (pc_offset() + kPcLoadDelta);

}

// Branch instructions.

void Assembler::b(int branch_offset, Condition cond) {

  ASSERT((branch_offset & 3) == 0);

  int imm24 = branch_offset >> 2;

  ASSERT(is_int24(imm24));

  emit(cond | B27 | B25 | (imm24 & kImm24Mask));

  if (cond == al) {

    // Dead code is a good location to emit the constant pool.

    CheckConstPool(false, false);

  }

}

void Assembler::bl(int branch_offset, Condition cond) {

  positions_recorder()->WriteRecordedPositions();

  ASSERT((branch_offset & 3) == 0);

  int imm24 = branch_offset >> 2;

  ASSERT(is_int24(imm24));

  emit(cond | B27 | B25 | B24 | (imm24 & kImm24Mask));

}

void Assembler::blx(int branch_offset) {  // v5 and above

  positions_recorder()->WriteRecordedPositions();

  ASSERT((branch_offset & 1) == 0);

  int h = ((branch_offset & 2) >> 1)*B24;

  int imm24 = branch_offset >> 2;

  ASSERT(is_int24(imm24));

  emit(kSpecialCondition | B27 | B25 | h | (imm24 & kImm24Mask));

}

void Assembler::blx(Register target, Condition cond) {  // v5 and above

  positions_recorder()->WriteRecordedPositions();

  ASSERT(!target.is(pc));

  emit(cond | B24 | B21 | 15*B16 | 15*B12 | 15*B8 | BLX | target.code());

}

void Assembler::bx(Register target, Condition cond) {  // v5 and above, plus v4t

  positions_recorder()->WriteRecordedPositions();

  ASSERT(!target.is(pc));  // use of pc is actually allowed, but discouraged

  emit(cond | B24 | B21 | 15*B16 | 15*B12 | 15*B8 | BX | target.code());

}

// Data-processing instructions.

void Assembler::and_(Register dst, Register src1, const Operand& src2,

                     SBit s, Condition cond) {

  addrmod1(cond | AND | s, src1, dst, src2);

}

void Assembler::eor(Register dst, Register src1, const Operand& src2,