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main_repo / deps / v8 / src / x64 / assembler-x64.cc @ f230a1cf
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// Copyright 2012 the V8 project authors. All rights reserved.
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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// * Neither the name of Google Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#include "v8.h" |
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#if V8_TARGET_ARCH_X64
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#include "macro-assembler.h" |
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#include "serialize.h" |
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namespace v8 {
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namespace internal {
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// -----------------------------------------------------------------------------
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// Implementation of CpuFeatures
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#ifdef DEBUG
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bool CpuFeatures::initialized_ = false; |
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#endif
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uint64_t CpuFeatures::supported_ = CpuFeatures::kDefaultCpuFeatures; |
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uint64_t CpuFeatures::found_by_runtime_probing_only_ = 0;
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uint64_t CpuFeatures::cross_compile_ = 0;
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ExternalReference ExternalReference::cpu_features() {
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ASSERT(CpuFeatures::initialized_); |
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return ExternalReference(&CpuFeatures::supported_);
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} |
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void CpuFeatures::Probe() {
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ASSERT(supported_ == CpuFeatures::kDefaultCpuFeatures); |
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#ifdef DEBUG
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initialized_ = true;
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#endif
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supported_ = kDefaultCpuFeatures; |
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if (Serializer::enabled()) {
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supported_ |= OS::CpuFeaturesImpliedByPlatform(); |
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return; // No features if we might serialize. |
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} |
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uint64_t probed_features = 0;
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CPU cpu; |
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if (cpu.has_sse41()) {
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probed_features |= static_cast<uint64_t>(1) << SSE4_1; |
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} |
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if (cpu.has_sse3()) {
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probed_features |= static_cast<uint64_t>(1) << SSE3; |
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} |
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// SSE2 must be available on every x64 CPU.
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ASSERT(cpu.has_sse2()); |
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probed_features |= static_cast<uint64_t>(1) << SSE2; |
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// CMOD must be available on every x64 CPU.
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ASSERT(cpu.has_cmov()); |
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probed_features |= static_cast<uint64_t>(1) << CMOV; |
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// SAHF is not generally available in long mode.
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if (cpu.has_sahf()) {
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probed_features |= static_cast<uint64_t>(1) << SAHF; |
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} |
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uint64_t platform_features = OS::CpuFeaturesImpliedByPlatform(); |
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supported_ = probed_features | platform_features; |
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found_by_runtime_probing_only_ |
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= probed_features & ~kDefaultCpuFeatures & ~platform_features; |
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} |
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// -----------------------------------------------------------------------------
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// Implementation of RelocInfo
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// Patch the code at the current PC with a call to the target address.
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// Additional guard int3 instructions can be added if required.
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void RelocInfo::PatchCodeWithCall(Address target, int guard_bytes) { |
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int code_size = Assembler::kCallSequenceLength + guard_bytes;
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// Create a code patcher.
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CodePatcher patcher(pc_, code_size); |
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// Add a label for checking the size of the code used for returning.
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#ifdef DEBUG
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Label check_codesize; |
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patcher.masm()->bind(&check_codesize); |
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#endif
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// Patch the code.
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patcher.masm()->movq(kScratchRegister, target, RelocInfo::NONE64); |
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patcher.masm()->call(kScratchRegister); |
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// Check that the size of the code generated is as expected.
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ASSERT_EQ(Assembler::kCallSequenceLength, |
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patcher.masm()->SizeOfCodeGeneratedSince(&check_codesize)); |
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// Add the requested number of int3 instructions after the call.
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for (int i = 0; i < guard_bytes; i++) { |
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patcher.masm()->int3(); |
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} |
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} |
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void RelocInfo::PatchCode(byte* instructions, int instruction_count) { |
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// Patch the code at the current address with the supplied instructions.
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for (int i = 0; i < instruction_count; i++) { |
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*(pc_ + i) = *(instructions + i); |
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} |
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// Indicate that code has changed.
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CPU::FlushICache(pc_, instruction_count); |
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} |
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// -----------------------------------------------------------------------------
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// Register constants.
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const int |
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Register::kRegisterCodeByAllocationIndex[kMaxNumAllocatableRegisters] = {
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// rax, rbx, rdx, rcx, rdi, r8, r9, r11, r14, r15
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0, 3, 2, 1, 7, 8, 9, 11, 14, 15 |
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}; |
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const int Register::kAllocationIndexByRegisterCode[kNumRegisters] = { |
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0, 3, 2, 1, -1, -1, -1, 4, 5, 6, -1, 7, -1, -1, 8, 9 |
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}; |
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// -----------------------------------------------------------------------------
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// Implementation of Operand
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Operand::Operand(Register base, int32_t disp) : rex_(0) {
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len_ = 1;
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if (base.is(rsp) || base.is(r12)) {
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// SIB byte is needed to encode (rsp + offset) or (r12 + offset).
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set_sib(times_1, rsp, base); |
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} |
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if (disp == 0 && !base.is(rbp) && !base.is(r13)) { |
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set_modrm(0, base);
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} else if (is_int8(disp)) { |
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set_modrm(1, base);
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set_disp8(disp); |
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} else {
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set_modrm(2, base);
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set_disp32(disp); |
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} |
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} |
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Operand::Operand(Register base, |
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Register index, |
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ScaleFactor scale, |
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int32_t disp) : rex_(0) {
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ASSERT(!index.is(rsp)); |
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len_ = 1;
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set_sib(scale, index, base); |
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if (disp == 0 && !base.is(rbp) && !base.is(r13)) { |
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// This call to set_modrm doesn't overwrite the REX.B (or REX.X) bits
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// possibly set by set_sib.
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set_modrm(0, rsp);
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} else if (is_int8(disp)) { |
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set_modrm(1, rsp);
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set_disp8(disp); |
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} else {
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set_modrm(2, rsp);
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set_disp32(disp); |
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} |
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} |
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Operand::Operand(Register index, |
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ScaleFactor scale, |
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int32_t disp) : rex_(0) {
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ASSERT(!index.is(rsp)); |
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len_ = 1;
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set_modrm(0, rsp);
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set_sib(scale, index, rbp); |
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set_disp32(disp); |
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} |
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Operand::Operand(const Operand& operand, int32_t offset) {
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ASSERT(operand.len_ >= 1);
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// Operand encodes REX ModR/M [SIB] [Disp].
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byte modrm = operand.buf_[0];
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ASSERT(modrm < 0xC0); // Disallow mode 3 (register target). |
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bool has_sib = ((modrm & 0x07) == 0x04); |
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byte mode = modrm & 0xC0;
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int disp_offset = has_sib ? 2 : 1; |
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int base_reg = (has_sib ? operand.buf_[1] : modrm) & 0x07; |
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// Mode 0 with rbp/r13 as ModR/M or SIB base register always has a 32-bit
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// displacement.
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bool is_baseless = (mode == 0) && (base_reg == 0x05); // No base or RIP base. |
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int32_t disp_value = 0;
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if (mode == 0x80 || is_baseless) { |
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// Mode 2 or mode 0 with rbp/r13 as base: Word displacement.
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disp_value = *BitCast<const int32_t*>(&operand.buf_[disp_offset]);
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} else if (mode == 0x40) { |
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// Mode 1: Byte displacement.
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disp_value = static_cast<signed char>(operand.buf_[disp_offset]); |
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} |
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// Write new operand with same registers, but with modified displacement.
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ASSERT(offset >= 0 ? disp_value + offset > disp_value
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: disp_value + offset < disp_value); // No overflow.
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disp_value += offset; |
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rex_ = operand.rex_; |
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if (!is_int8(disp_value) || is_baseless) {
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// Need 32 bits of displacement, mode 2 or mode 1 with register rbp/r13.
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buf_[0] = (modrm & 0x3f) | (is_baseless ? 0x00 : 0x80); |
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len_ = disp_offset + 4;
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Memory::int32_at(&buf_[disp_offset]) = disp_value; |
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} else if (disp_value != 0 || (base_reg == 0x05)) { |
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// Need 8 bits of displacement.
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buf_[0] = (modrm & 0x3f) | 0x40; // Mode 1. |
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len_ = disp_offset + 1;
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buf_[disp_offset] = static_cast<byte>(disp_value);
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} else {
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// Need no displacement.
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buf_[0] = (modrm & 0x3f); // Mode 0. |
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len_ = disp_offset; |
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} |
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if (has_sib) {
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buf_[1] = operand.buf_[1]; |
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} |
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} |
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bool Operand::AddressUsesRegister(Register reg) const { |
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int code = reg.code();
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ASSERT((buf_[0] & 0xC0) != 0xC0); // Always a memory operand. |
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// Start with only low three bits of base register. Initial decoding doesn't
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// distinguish on the REX.B bit.
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int base_code = buf_[0] & 0x07; |
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if (base_code == rsp.code()) {
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// SIB byte present in buf_[1].
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// Check the index register from the SIB byte + REX.X prefix.
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int index_code = ((buf_[1] >> 3) & 0x07) | ((rex_ & 0x02) << 2); |
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// Index code (including REX.X) of 0x04 (rsp) means no index register.
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if (index_code != rsp.code() && index_code == code) return true; |
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// Add REX.B to get the full base register code.
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base_code = (buf_[1] & 0x07) | ((rex_ & 0x01) << 3); |
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// A base register of 0x05 (rbp) with mod = 0 means no base register.
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if (base_code == rbp.code() && ((buf_[0] & 0xC0) == 0)) return false; |
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return code == base_code;
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} else {
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// A base register with low bits of 0x05 (rbp or r13) and mod = 0 means
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// no base register.
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if (base_code == rbp.code() && ((buf_[0] & 0xC0) == 0)) return false; |
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base_code |= ((rex_ & 0x01) << 3); |
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return code == base_code;
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} |
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} |
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// -----------------------------------------------------------------------------
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// Implementation of Assembler.
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#ifdef GENERATED_CODE_COVERAGE
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static void InitCoverageLog(); |
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#endif
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Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size) |
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: AssemblerBase(isolate, buffer, buffer_size), |
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code_targets_(100),
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positions_recorder_(this) {
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// Clear the buffer in debug mode unless it was provided by the
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// caller in which case we can't be sure it's okay to overwrite
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// existing code in it.
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#ifdef DEBUG
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if (own_buffer_) {
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memset(buffer_, 0xCC, buffer_size_); // int3 |
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} |
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#endif
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reloc_info_writer.Reposition(buffer_ + buffer_size_, pc_); |
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#ifdef GENERATED_CODE_COVERAGE
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InitCoverageLog(); |
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#endif
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} |
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void Assembler::GetCode(CodeDesc* desc) {
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// Finalize code (at this point overflow() may be true, but the gap ensures
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// that we are still not overlapping instructions and relocation info).
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ASSERT(pc_ <= reloc_info_writer.pos()); // No overlap.
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// Set up code descriptor.
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desc->buffer = buffer_; |
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desc->buffer_size = buffer_size_; |
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desc->instr_size = pc_offset(); |
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ASSERT(desc->instr_size > 0); // Zero-size code objects upset the system. |
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desc->reloc_size = |
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static_cast<int>((buffer_ + buffer_size_) - reloc_info_writer.pos()); |
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desc->origin = this;
|
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} |
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|
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|
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void Assembler::Align(int m) { |
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ASSERT(IsPowerOf2(m)); |
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int delta = (m - (pc_offset() & (m - 1))) & (m - 1); |
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Nop(delta); |
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} |
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|
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|
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void Assembler::CodeTargetAlign() {
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Align(16); // Preferred alignment of jump targets on x64. |
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} |
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|
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|
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bool Assembler::IsNop(Address addr) {
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Address a = addr; |
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while (*a == 0x66) a++; |
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if (*a == 0x90) return true; |
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if (a[0] == 0xf && a[1] == 0x1f) return true; |
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return false; |
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} |
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|
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|
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void Assembler::bind_to(Label* L, int pos) { |
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ASSERT(!L->is_bound()); // Label may only be bound once.
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ASSERT(0 <= pos && pos <= pc_offset()); // Position must be valid. |
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if (L->is_linked()) {
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int current = L->pos();
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int next = long_at(current);
|
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while (next != current) {
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// Relative address, relative to point after address.
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int imm32 = pos - (current + sizeof(int32_t)); |
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long_at_put(current, imm32); |
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current = next; |
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next = long_at(next); |
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} |
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// Fix up last fixup on linked list.
|
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int last_imm32 = pos - (current + sizeof(int32_t)); |
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long_at_put(current, last_imm32); |
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} |
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while (L->is_near_linked()) {
|
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int fixup_pos = L->near_link_pos();
|
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int offset_to_next =
|
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static_cast<int>(*reinterpret_cast<int8_t*>(addr_at(fixup_pos))); |
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ASSERT(offset_to_next <= 0);
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int disp = pos - (fixup_pos + sizeof(int8_t)); |
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CHECK(is_int8(disp)); |
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set_byte_at(fixup_pos, disp); |
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if (offset_to_next < 0) { |
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L->link_to(fixup_pos + offset_to_next, Label::kNear); |
| 372 |
} else {
|
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L->UnuseNear(); |
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} |
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} |
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L->bind_to(pos); |
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} |
| 378 |
|
| 379 |
|
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void Assembler::bind(Label* L) {
|
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bind_to(L, pc_offset()); |
| 382 |
} |
| 383 |
|
| 384 |
|
| 385 |
void Assembler::GrowBuffer() {
|
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ASSERT(buffer_overflow()); |
| 387 |
if (!own_buffer_) FATAL("external code buffer is too small"); |
| 388 |
|
| 389 |
// Compute new buffer size.
|
| 390 |
CodeDesc desc; // the new buffer
|
| 391 |
if (buffer_size_ < 4*KB) { |
| 392 |
desc.buffer_size = 4*KB;
|
| 393 |
} else {
|
| 394 |
desc.buffer_size = 2*buffer_size_;
|
| 395 |
} |
| 396 |
// Some internal data structures overflow for very large buffers,
|
| 397 |
// they must ensure that kMaximalBufferSize is not too large.
|
| 398 |
if ((desc.buffer_size > kMaximalBufferSize) ||
|
| 399 |
(desc.buffer_size > isolate()->heap()->MaxOldGenerationSize())) {
|
| 400 |
V8::FatalProcessOutOfMemory("Assembler::GrowBuffer");
|
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} |
| 402 |
|
| 403 |
// Set up new buffer.
|
| 404 |
desc.buffer = NewArray<byte>(desc.buffer_size); |
| 405 |
desc.instr_size = pc_offset(); |
| 406 |
desc.reloc_size = |
| 407 |
static_cast<int>((buffer_ + buffer_size_) - (reloc_info_writer.pos())); |
| 408 |
|
| 409 |
// Clear the buffer in debug mode. Use 'int3' instructions to make
|
| 410 |
// sure to get into problems if we ever run uninitialized code.
|
| 411 |
#ifdef DEBUG
|
| 412 |
memset(desc.buffer, 0xCC, desc.buffer_size);
|
| 413 |
#endif
|
| 414 |
|
| 415 |
// Copy the data.
|
| 416 |
intptr_t pc_delta = desc.buffer - buffer_; |
| 417 |
intptr_t rc_delta = (desc.buffer + desc.buffer_size) - |
| 418 |
(buffer_ + buffer_size_); |
| 419 |
OS::MemMove(desc.buffer, buffer_, desc.instr_size); |
| 420 |
OS::MemMove(rc_delta + reloc_info_writer.pos(), |
| 421 |
reloc_info_writer.pos(), desc.reloc_size); |
| 422 |
|
| 423 |
// Switch buffers.
|
| 424 |
if (isolate() != NULL && |
| 425 |
isolate()->assembler_spare_buffer() == NULL &&
|
| 426 |
buffer_size_ == kMinimalBufferSize) {
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isolate()->set_assembler_spare_buffer(buffer_); |
| 428 |
} else {
|
| 429 |
DeleteArray(buffer_); |
| 430 |
} |
| 431 |
buffer_ = desc.buffer; |
| 432 |
buffer_size_ = desc.buffer_size; |
| 433 |
pc_ += pc_delta; |
| 434 |
reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta, |
| 435 |
reloc_info_writer.last_pc() + pc_delta); |
| 436 |
|
| 437 |
// Relocate runtime entries.
|
| 438 |
for (RelocIterator it(desc); !it.done(); it.next()) {
|
| 439 |
RelocInfo::Mode rmode = it.rinfo()->rmode(); |
| 440 |
if (rmode == RelocInfo::INTERNAL_REFERENCE) {
|
| 441 |
intptr_t* p = reinterpret_cast<intptr_t*>(it.rinfo()->pc());
|
| 442 |
if (*p != 0) { // 0 means uninitialized. |
| 443 |
*p += pc_delta; |
| 444 |
} |
| 445 |
} |
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} |
| 447 |
|
| 448 |
ASSERT(!buffer_overflow()); |
| 449 |
} |
| 450 |
|
| 451 |
|
| 452 |
void Assembler::emit_operand(int code, const Operand& adr) { |
| 453 |
ASSERT(is_uint3(code)); |
| 454 |
const unsigned length = adr.len_; |
| 455 |
ASSERT(length > 0);
|
| 456 |
|
| 457 |
// Emit updated ModR/M byte containing the given register.
|
| 458 |
ASSERT((adr.buf_[0] & 0x38) == 0); |
| 459 |
pc_[0] = adr.buf_[0] | code << 3; |
| 460 |
|
| 461 |
// Emit the rest of the encoded operand.
|
| 462 |
for (unsigned i = 1; i < length; i++) pc_[i] = adr.buf_[i]; |
| 463 |
pc_ += length; |
| 464 |
} |
| 465 |
|
| 466 |
|
| 467 |
// Assembler Instruction implementations.
|
| 468 |
|
| 469 |
void Assembler::arithmetic_op(byte opcode, Register reg, const Operand& op) { |
| 470 |
EnsureSpace ensure_space(this);
|
| 471 |
emit_rex_64(reg, op); |
| 472 |
emit(opcode); |
| 473 |
emit_operand(reg, op); |
| 474 |
} |
| 475 |
|
| 476 |
|
| 477 |
void Assembler::arithmetic_op(byte opcode, Register reg, Register rm_reg) {
|
| 478 |
EnsureSpace ensure_space(this);
|
| 479 |
ASSERT((opcode & 0xC6) == 2); |
| 480 |
if (rm_reg.low_bits() == 4) { // Forces SIB byte. |
| 481 |
// Swap reg and rm_reg and change opcode operand order.
|
| 482 |
emit_rex_64(rm_reg, reg); |
| 483 |
emit(opcode ^ 0x02);
|
| 484 |
emit_modrm(rm_reg, reg); |
| 485 |
} else {
|
| 486 |
emit_rex_64(reg, rm_reg); |
| 487 |
emit(opcode); |
| 488 |
emit_modrm(reg, rm_reg); |
| 489 |
} |
| 490 |
} |
| 491 |
|
| 492 |
|
| 493 |
void Assembler::arithmetic_op_16(byte opcode, Register reg, Register rm_reg) {
|
| 494 |
EnsureSpace ensure_space(this);
|
| 495 |
ASSERT((opcode & 0xC6) == 2); |
| 496 |
if (rm_reg.low_bits() == 4) { // Forces SIB byte. |
| 497 |
// Swap reg and rm_reg and change opcode operand order.
|
| 498 |
emit(0x66);
|
| 499 |
emit_optional_rex_32(rm_reg, reg); |
| 500 |
emit(opcode ^ 0x02);
|
| 501 |
emit_modrm(rm_reg, reg); |
| 502 |
} else {
|
| 503 |
emit(0x66);
|
| 504 |
emit_optional_rex_32(reg, rm_reg); |
| 505 |
emit(opcode); |
| 506 |
emit_modrm(reg, rm_reg); |
| 507 |
} |
| 508 |
} |
| 509 |
|
| 510 |
|
| 511 |
void Assembler::arithmetic_op_16(byte opcode,
|
| 512 |
Register reg, |
| 513 |
const Operand& rm_reg) {
|
| 514 |
EnsureSpace ensure_space(this);
|
| 515 |
emit(0x66);
|
| 516 |
emit_optional_rex_32(reg, rm_reg); |
| 517 |
emit(opcode); |
| 518 |
emit_operand(reg, rm_reg); |
| 519 |
} |
| 520 |
|
| 521 |
|
| 522 |
void Assembler::arithmetic_op_32(byte opcode, Register reg, Register rm_reg) {
|
| 523 |
EnsureSpace ensure_space(this);
|
| 524 |
ASSERT((opcode & 0xC6) == 2); |
| 525 |
if (rm_reg.low_bits() == 4) { // Forces SIB byte. |
| 526 |
// Swap reg and rm_reg and change opcode operand order.
|
| 527 |
emit_optional_rex_32(rm_reg, reg); |
| 528 |
emit(opcode ^ 0x02); // E.g. 0x03 -> 0x01 for ADD. |
| 529 |
emit_modrm(rm_reg, reg); |
| 530 |
} else {
|
| 531 |
emit_optional_rex_32(reg, rm_reg); |
| 532 |
emit(opcode); |
| 533 |
emit_modrm(reg, rm_reg); |
| 534 |
} |
| 535 |
} |
| 536 |
|
| 537 |
|
| 538 |
void Assembler::arithmetic_op_32(byte opcode,
|
| 539 |
Register reg, |
| 540 |
const Operand& rm_reg) {
|
| 541 |
EnsureSpace ensure_space(this);
|
| 542 |
emit_optional_rex_32(reg, rm_reg); |
| 543 |
emit(opcode); |
| 544 |
emit_operand(reg, rm_reg); |
| 545 |
} |
| 546 |
|
| 547 |
|
| 548 |
void Assembler::immediate_arithmetic_op(byte subcode,
|
| 549 |
Register dst, |
| 550 |
Immediate src) {
|
| 551 |
EnsureSpace ensure_space(this);
|
| 552 |
emit_rex_64(dst); |
| 553 |
if (is_int8(src.value_)) {
|
| 554 |
emit(0x83);
|
| 555 |
emit_modrm(subcode, dst); |
| 556 |
emit(src.value_); |
| 557 |
} else if (dst.is(rax)) { |
| 558 |
emit(0x05 | (subcode << 3)); |
| 559 |
emitl(src.value_); |
| 560 |
} else {
|
| 561 |
emit(0x81);
|
| 562 |
emit_modrm(subcode, dst); |
| 563 |
emitl(src.value_); |
| 564 |
} |
| 565 |
} |
| 566 |
|
| 567 |
void Assembler::immediate_arithmetic_op(byte subcode,
|
| 568 |
const Operand& dst,
|
| 569 |
Immediate src) {
|
| 570 |
EnsureSpace ensure_space(this);
|
| 571 |
emit_rex_64(dst); |
| 572 |
if (is_int8(src.value_)) {
|
| 573 |
emit(0x83);
|
| 574 |
emit_operand(subcode, dst); |
| 575 |
emit(src.value_); |
| 576 |
} else {
|
| 577 |
emit(0x81);
|
| 578 |
emit_operand(subcode, dst); |
| 579 |
emitl(src.value_); |
| 580 |
} |
| 581 |
} |
| 582 |
|
| 583 |
|
| 584 |
void Assembler::immediate_arithmetic_op_16(byte subcode,
|
| 585 |
Register dst, |
| 586 |
Immediate src) {
|
| 587 |
EnsureSpace ensure_space(this);
|
| 588 |
emit(0x66); // Operand size override prefix. |
| 589 |
emit_optional_rex_32(dst); |
| 590 |
if (is_int8(src.value_)) {
|
| 591 |
emit(0x83);
|
| 592 |
emit_modrm(subcode, dst); |
| 593 |
emit(src.value_); |
| 594 |
} else if (dst.is(rax)) { |
| 595 |
emit(0x05 | (subcode << 3)); |
| 596 |
emitw(src.value_); |
| 597 |
} else {
|
| 598 |
emit(0x81);
|
| 599 |
emit_modrm(subcode, dst); |
| 600 |
emitw(src.value_); |
| 601 |
} |
| 602 |
} |
| 603 |
|
| 604 |
|
| 605 |
void Assembler::immediate_arithmetic_op_16(byte subcode,
|
| 606 |
const Operand& dst,
|
| 607 |
Immediate src) {
|
| 608 |
EnsureSpace ensure_space(this);
|
| 609 |
emit(0x66); // Operand size override prefix. |
| 610 |
emit_optional_rex_32(dst); |
| 611 |
if (is_int8(src.value_)) {
|
| 612 |
emit(0x83);
|
| 613 |
emit_operand(subcode, dst); |
| 614 |
emit(src.value_); |
| 615 |
} else {
|
| 616 |
emit(0x81);
|
| 617 |
emit_operand(subcode, dst); |
| 618 |
emitw(src.value_); |
| 619 |
} |
| 620 |
} |
| 621 |
|
| 622 |
|
| 623 |
void Assembler::immediate_arithmetic_op_32(byte subcode,
|
| 624 |
Register dst, |
| 625 |
Immediate src) {
|
| 626 |
EnsureSpace ensure_space(this);
|
| 627 |
emit_optional_rex_32(dst); |
| 628 |
if (is_int8(src.value_)) {
|
| 629 |
emit(0x83);
|
| 630 |
emit_modrm(subcode, dst); |
| 631 |
emit(src.value_); |
| 632 |
} else if (dst.is(rax)) { |
| 633 |
emit(0x05 | (subcode << 3)); |
| 634 |
emitl(src.value_); |
| 635 |
} else {
|
| 636 |
emit(0x81);
|
| 637 |
emit_modrm(subcode, dst); |
| 638 |
emitl(src.value_); |
| 639 |
} |
| 640 |
} |
| 641 |
|
| 642 |
|
| 643 |
void Assembler::immediate_arithmetic_op_32(byte subcode,
|
| 644 |
const Operand& dst,
|
| 645 |
Immediate src) {
|
| 646 |
EnsureSpace ensure_space(this);
|
| 647 |
emit_optional_rex_32(dst); |
| 648 |
if (is_int8(src.value_)) {
|
| 649 |
emit(0x83);
|
| 650 |
emit_operand(subcode, dst); |
| 651 |
emit(src.value_); |
| 652 |
} else {
|
| 653 |
emit(0x81);
|
| 654 |
emit_operand(subcode, dst); |
| 655 |
emitl(src.value_); |
| 656 |
} |
| 657 |
} |
| 658 |
|
| 659 |
|
| 660 |
void Assembler::immediate_arithmetic_op_8(byte subcode,
|
| 661 |
const Operand& dst,
|
| 662 |
Immediate src) {
|
| 663 |
EnsureSpace ensure_space(this);
|
| 664 |
emit_optional_rex_32(dst); |
| 665 |
ASSERT(is_int8(src.value_) || is_uint8(src.value_)); |
| 666 |
emit(0x80);
|
| 667 |
emit_operand(subcode, dst); |
| 668 |
emit(src.value_); |
| 669 |
} |
| 670 |
|
| 671 |
|
| 672 |
void Assembler::immediate_arithmetic_op_8(byte subcode,
|
| 673 |
Register dst, |
| 674 |
Immediate src) {
|
| 675 |
EnsureSpace ensure_space(this);
|
| 676 |
if (!dst.is_byte_register()) {
|
| 677 |
// Use 64-bit mode byte registers.
|
| 678 |
emit_rex_64(dst); |
| 679 |
} |
| 680 |
ASSERT(is_int8(src.value_) || is_uint8(src.value_)); |
| 681 |
emit(0x80);
|
| 682 |
emit_modrm(subcode, dst); |
| 683 |
emit(src.value_); |
| 684 |
} |
| 685 |
|
| 686 |
|
| 687 |
void Assembler::shift(Register dst, Immediate shift_amount, int subcode) { |
| 688 |
EnsureSpace ensure_space(this);
|
| 689 |
ASSERT(is_uint6(shift_amount.value_)); // illegal shift count
|
| 690 |
if (shift_amount.value_ == 1) { |
| 691 |
emit_rex_64(dst); |
| 692 |
emit(0xD1);
|
| 693 |
emit_modrm(subcode, dst); |
| 694 |
} else {
|
| 695 |
emit_rex_64(dst); |
| 696 |
emit(0xC1);
|
| 697 |
emit_modrm(subcode, dst); |
| 698 |
emit(shift_amount.value_); |
| 699 |
} |
| 700 |
} |
| 701 |
|
| 702 |
|
| 703 |
void Assembler::shift(Register dst, int subcode) { |
| 704 |
EnsureSpace ensure_space(this);
|
| 705 |
emit_rex_64(dst); |
| 706 |
emit(0xD3);
|
| 707 |
emit_modrm(subcode, dst); |
| 708 |
} |
| 709 |
|
| 710 |
|
| 711 |
void Assembler::shift_32(Register dst, int subcode) { |
| 712 |
EnsureSpace ensure_space(this);
|
| 713 |
emit_optional_rex_32(dst); |
| 714 |
emit(0xD3);
|
| 715 |
emit_modrm(subcode, dst); |
| 716 |
} |
| 717 |
|
| 718 |
|
| 719 |
void Assembler::shift_32(Register dst, Immediate shift_amount, int subcode) { |
| 720 |
EnsureSpace ensure_space(this);
|
| 721 |
ASSERT(is_uint5(shift_amount.value_)); // illegal shift count
|
| 722 |
if (shift_amount.value_ == 1) { |
| 723 |
emit_optional_rex_32(dst); |
| 724 |
emit(0xD1);
|
| 725 |
emit_modrm(subcode, dst); |
| 726 |
} else {
|
| 727 |
emit_optional_rex_32(dst); |
| 728 |
emit(0xC1);
|
| 729 |
emit_modrm(subcode, dst); |
| 730 |
emit(shift_amount.value_); |
| 731 |
} |
| 732 |
} |
| 733 |
|
| 734 |
|
| 735 |
void Assembler::bt(const Operand& dst, Register src) { |
| 736 |
EnsureSpace ensure_space(this);
|
| 737 |
emit_rex_64(src, dst); |
| 738 |
emit(0x0F);
|
| 739 |
emit(0xA3);
|
| 740 |
emit_operand(src, dst); |
| 741 |
} |
| 742 |
|
| 743 |
|
| 744 |
void Assembler::bts(const Operand& dst, Register src) { |
| 745 |
EnsureSpace ensure_space(this);
|
| 746 |
emit_rex_64(src, dst); |
| 747 |
emit(0x0F);
|
| 748 |
emit(0xAB);
|
| 749 |
emit_operand(src, dst); |
| 750 |
} |
| 751 |
|
| 752 |
|
| 753 |
void Assembler::call(Label* L) {
|
| 754 |
positions_recorder()->WriteRecordedPositions(); |
| 755 |
EnsureSpace ensure_space(this);
|
| 756 |
// 1110 1000 #32-bit disp.
|
| 757 |
emit(0xE8);
|
| 758 |
if (L->is_bound()) {
|
| 759 |
int offset = L->pos() - pc_offset() - sizeof(int32_t); |
| 760 |
ASSERT(offset <= 0);
|
| 761 |
emitl(offset); |
| 762 |
} else if (L->is_linked()) { |
| 763 |
emitl(L->pos()); |
| 764 |
L->link_to(pc_offset() - sizeof(int32_t));
|
| 765 |
} else {
|
| 766 |
ASSERT(L->is_unused()); |
| 767 |
int32_t current = pc_offset(); |
| 768 |
emitl(current); |
| 769 |
L->link_to(current); |
| 770 |
} |
| 771 |
} |
| 772 |
|
| 773 |
|
| 774 |
void Assembler::call(Address entry, RelocInfo::Mode rmode) {
|
| 775 |
ASSERT(RelocInfo::IsRuntimeEntry(rmode)); |
| 776 |
positions_recorder()->WriteRecordedPositions(); |
| 777 |
EnsureSpace ensure_space(this);
|
| 778 |
// 1110 1000 #32-bit disp.
|
| 779 |
emit(0xE8);
|
| 780 |
emit_runtime_entry(entry, rmode); |
| 781 |
} |
| 782 |
|
| 783 |
|
| 784 |
void Assembler::call(Handle<Code> target,
|
| 785 |
RelocInfo::Mode rmode, |
| 786 |
TypeFeedbackId ast_id) {
|
| 787 |
positions_recorder()->WriteRecordedPositions(); |
| 788 |
EnsureSpace ensure_space(this);
|
| 789 |
// 1110 1000 #32-bit disp.
|
| 790 |
emit(0xE8);
|
| 791 |
emit_code_target(target, rmode, ast_id); |
| 792 |
} |
| 793 |
|
| 794 |
|
| 795 |
void Assembler::call(Register adr) {
|
| 796 |
positions_recorder()->WriteRecordedPositions(); |
| 797 |
EnsureSpace ensure_space(this);
|
| 798 |
// Opcode: FF /2 r64.
|
| 799 |
emit_optional_rex_32(adr); |
| 800 |
emit(0xFF);
|
| 801 |
emit_modrm(0x2, adr);
|
| 802 |
} |
| 803 |
|
| 804 |
|
| 805 |
void Assembler::call(const Operand& op) { |
| 806 |
positions_recorder()->WriteRecordedPositions(); |
| 807 |
EnsureSpace ensure_space(this);
|
| 808 |
// Opcode: FF /2 m64.
|
| 809 |
emit_optional_rex_32(op); |
| 810 |
emit(0xFF);
|
| 811 |
emit_operand(0x2, op);
|
| 812 |
} |
| 813 |
|
| 814 |
|
| 815 |
// Calls directly to the given address using a relative offset.
|
| 816 |
// Should only ever be used in Code objects for calls within the
|
| 817 |
// same Code object. Should not be used when generating new code (use labels),
|
| 818 |
// but only when patching existing code.
|
| 819 |
void Assembler::call(Address target) {
|
| 820 |
positions_recorder()->WriteRecordedPositions(); |
| 821 |
EnsureSpace ensure_space(this);
|
| 822 |
// 1110 1000 #32-bit disp.
|
| 823 |
emit(0xE8);
|
| 824 |
Address source = pc_ + 4;
|
| 825 |
intptr_t displacement = target - source; |
| 826 |
ASSERT(is_int32(displacement)); |
| 827 |
emitl(static_cast<int32_t>(displacement));
|
| 828 |
} |
| 829 |
|
| 830 |
|
| 831 |
void Assembler::clc() {
|
| 832 |
EnsureSpace ensure_space(this);
|
| 833 |
emit(0xF8);
|
| 834 |
} |
| 835 |
|
| 836 |
|
| 837 |
void Assembler::cld() {
|
| 838 |
EnsureSpace ensure_space(this);
|
| 839 |
emit(0xFC);
|
| 840 |
} |
| 841 |
|
| 842 |
|
| 843 |
void Assembler::cdq() {
|
| 844 |
EnsureSpace ensure_space(this);
|
| 845 |
emit(0x99);
|
| 846 |
} |
| 847 |
|
| 848 |
|
| 849 |
void Assembler::cmovq(Condition cc, Register dst, Register src) {
|
| 850 |
if (cc == always) {
|
| 851 |
movq(dst, src); |
| 852 |
} else if (cc == never) { |
| 853 |
return;
|
| 854 |
} |
| 855 |
// No need to check CpuInfo for CMOV support, it's a required part of the
|
| 856 |
// 64-bit architecture.
|
| 857 |
ASSERT(cc >= 0); // Use mov for unconditional moves. |
| 858 |
EnsureSpace ensure_space(this);
|
| 859 |
// Opcode: REX.W 0f 40 + cc /r.
|
| 860 |
emit_rex_64(dst, src); |
| 861 |
emit(0x0f);
|
| 862 |
emit(0x40 + cc);
|
| 863 |
emit_modrm(dst, src); |
| 864 |
} |
| 865 |
|
| 866 |
|
| 867 |
void Assembler::cmovq(Condition cc, Register dst, const Operand& src) { |
| 868 |
if (cc == always) {
|
| 869 |
movq(dst, src); |
| 870 |
} else if (cc == never) { |
| 871 |
return;
|
| 872 |
} |
| 873 |
ASSERT(cc >= 0);
|
| 874 |
EnsureSpace ensure_space(this);
|
| 875 |
// Opcode: REX.W 0f 40 + cc /r.
|
| 876 |
emit_rex_64(dst, src); |
| 877 |
emit(0x0f);
|
| 878 |
emit(0x40 + cc);
|
| 879 |
emit_operand(dst, src); |
| 880 |
} |
| 881 |
|
| 882 |
|
| 883 |
void Assembler::cmovl(Condition cc, Register dst, Register src) {
|
| 884 |
if (cc == always) {
|
| 885 |
movl(dst, src); |
| 886 |
} else if (cc == never) { |
| 887 |
return;
|
| 888 |
} |
| 889 |
ASSERT(cc >= 0);
|
| 890 |
EnsureSpace ensure_space(this);
|
| 891 |
// Opcode: 0f 40 + cc /r.
|
| 892 |
emit_optional_rex_32(dst, src); |
| 893 |
emit(0x0f);
|
| 894 |
emit(0x40 + cc);
|
| 895 |
emit_modrm(dst, src); |
| 896 |
} |
| 897 |
|
| 898 |
|
| 899 |
void Assembler::cmovl(Condition cc, Register dst, const Operand& src) { |
| 900 |
if (cc == always) {
|
| 901 |
movl(dst, src); |
| 902 |
} else if (cc == never) { |
| 903 |
return;
|
| 904 |
} |
| 905 |
ASSERT(cc >= 0);
|
| 906 |
EnsureSpace ensure_space(this);
|
| 907 |
// Opcode: 0f 40 + cc /r.
|
| 908 |
emit_optional_rex_32(dst, src); |
| 909 |
emit(0x0f);
|
| 910 |
emit(0x40 + cc);
|
| 911 |
emit_operand(dst, src); |
| 912 |
} |
| 913 |
|
| 914 |
|
| 915 |
void Assembler::cmpb_al(Immediate imm8) {
|
| 916 |
ASSERT(is_int8(imm8.value_) || is_uint8(imm8.value_)); |
| 917 |
EnsureSpace ensure_space(this);
|
| 918 |
emit(0x3c);
|
| 919 |
emit(imm8.value_); |
| 920 |
} |
| 921 |
|
| 922 |
|
| 923 |
void Assembler::cpuid() {
|
| 924 |
EnsureSpace ensure_space(this);
|
| 925 |
emit(0x0F);
|
| 926 |
emit(0xA2);
|
| 927 |
} |
| 928 |
|
| 929 |
|
| 930 |
void Assembler::cqo() {
|
| 931 |
EnsureSpace ensure_space(this);
|
| 932 |
emit_rex_64(); |
| 933 |
emit(0x99);
|
| 934 |
} |
| 935 |
|
| 936 |
|
| 937 |
void Assembler::decq(Register dst) {
|
| 938 |
EnsureSpace ensure_space(this);
|
| 939 |
emit_rex_64(dst); |
| 940 |
emit(0xFF);
|
| 941 |
emit_modrm(0x1, dst);
|
| 942 |
} |
| 943 |
|
| 944 |
|
| 945 |
void Assembler::decq(const Operand& dst) { |
| 946 |
EnsureSpace ensure_space(this);
|
| 947 |
emit_rex_64(dst); |
| 948 |
emit(0xFF);
|
| 949 |
emit_operand(1, dst);
|
| 950 |
} |
| 951 |
|
| 952 |
|
| 953 |
void Assembler::decl(Register dst) {
|
| 954 |
EnsureSpace ensure_space(this);
|
| 955 |
emit_optional_rex_32(dst); |
| 956 |
emit(0xFF);
|
| 957 |
emit_modrm(0x1, dst);
|
| 958 |
} |
| 959 |
|
| 960 |
|
| 961 |
void Assembler::decl(const Operand& dst) { |
| 962 |
EnsureSpace ensure_space(this);
|
| 963 |
emit_optional_rex_32(dst); |
| 964 |
emit(0xFF);
|
| 965 |
emit_operand(1, dst);
|
| 966 |
} |
| 967 |
|
| 968 |
|
| 969 |
void Assembler::decb(Register dst) {
|
| 970 |
EnsureSpace ensure_space(this);
|
| 971 |
if (!dst.is_byte_register()) {
|
| 972 |
// Register is not one of al, bl, cl, dl. Its encoding needs REX.
|
| 973 |
emit_rex_32(dst); |
| 974 |
} |
| 975 |
emit(0xFE);
|
| 976 |
emit_modrm(0x1, dst);
|
| 977 |
} |
| 978 |
|
| 979 |
|
| 980 |
void Assembler::decb(const Operand& dst) { |
| 981 |
EnsureSpace ensure_space(this);
|
| 982 |
emit_optional_rex_32(dst); |
| 983 |
emit(0xFE);
|
| 984 |
emit_operand(1, dst);
|
| 985 |
} |
| 986 |
|
| 987 |
|
| 988 |
void Assembler::enter(Immediate size) {
|
| 989 |
EnsureSpace ensure_space(this);
|
| 990 |
emit(0xC8);
|
| 991 |
emitw(size.value_); // 16 bit operand, always.
|
| 992 |
emit(0);
|
| 993 |
} |
| 994 |
|
| 995 |
|
| 996 |
void Assembler::hlt() {
|
| 997 |
EnsureSpace ensure_space(this);
|
| 998 |
emit(0xF4);
|
| 999 |
} |
| 1000 |
|
| 1001 |
|
| 1002 |
void Assembler::idivq(Register src) {
|
| 1003 |
EnsureSpace ensure_space(this);
|
| 1004 |
emit_rex_64(src); |
| 1005 |
emit(0xF7);
|
| 1006 |
emit_modrm(0x7, src);
|
| 1007 |
} |
| 1008 |
|
| 1009 |
|
| 1010 |
void Assembler::idivl(Register src) {
|
| 1011 |
EnsureSpace ensure_space(this);
|
| 1012 |
emit_optional_rex_32(src); |
| 1013 |
emit(0xF7);
|
| 1014 |
emit_modrm(0x7, src);
|
| 1015 |
} |
| 1016 |
|
| 1017 |
|
| 1018 |
void Assembler::imul(Register src) {
|
| 1019 |
EnsureSpace ensure_space(this);
|
| 1020 |
emit_rex_64(src); |
| 1021 |
emit(0xF7);
|
| 1022 |
emit_modrm(0x5, src);
|
| 1023 |
} |
| 1024 |
|
| 1025 |
|
| 1026 |
void Assembler::imul(Register dst, Register src) {
|
| 1027 |
EnsureSpace ensure_space(this);
|
| 1028 |
emit_rex_64(dst, src); |
| 1029 |
emit(0x0F);
|
| 1030 |
emit(0xAF);
|
| 1031 |
emit_modrm(dst, src); |
| 1032 |
} |
| 1033 |
|
| 1034 |
|
| 1035 |
void Assembler::imul(Register dst, const Operand& src) { |
| 1036 |
EnsureSpace ensure_space(this);
|
| 1037 |
emit_rex_64(dst, src); |
| 1038 |
emit(0x0F);
|
| 1039 |
emit(0xAF);
|
| 1040 |
emit_operand(dst, src); |
| 1041 |
} |
| 1042 |
|
| 1043 |
|
| 1044 |
void Assembler::imul(Register dst, Register src, Immediate imm) {
|
| 1045 |
EnsureSpace ensure_space(this);
|
| 1046 |
emit_rex_64(dst, src); |
| 1047 |
if (is_int8(imm.value_)) {
|
| 1048 |
emit(0x6B);
|
| 1049 |
emit_modrm(dst, src); |
| 1050 |
emit(imm.value_); |
| 1051 |
} else {
|
| 1052 |
emit(0x69);
|
| 1053 |
emit_modrm(dst, src); |
| 1054 |
emitl(imm.value_); |
| 1055 |
} |
| 1056 |
} |
| 1057 |
|
| 1058 |
|
| 1059 |
void Assembler::imull(Register dst, Register src) {
|
| 1060 |
EnsureSpace ensure_space(this);
|
| 1061 |
emit_optional_rex_32(dst, src); |
| 1062 |
emit(0x0F);
|
| 1063 |
emit(0xAF);
|
| 1064 |
emit_modrm(dst, src); |
| 1065 |
} |
| 1066 |
|
| 1067 |
|
| 1068 |
void Assembler::imull(Register dst, const Operand& src) { |
| 1069 |
EnsureSpace ensure_space(this);
|
| 1070 |
emit_optional_rex_32(dst, src); |
| 1071 |
emit(0x0F);
|
| 1072 |
emit(0xAF);
|
| 1073 |
emit_operand(dst, src); |
| 1074 |
} |
| 1075 |
|
| 1076 |
|
| 1077 |
void Assembler::imull(Register dst, Register src, Immediate imm) {
|
| 1078 |
EnsureSpace ensure_space(this);
|
| 1079 |
emit_optional_rex_32(dst, src); |
| 1080 |
if (is_int8(imm.value_)) {
|
| 1081 |
emit(0x6B);
|
| 1082 |
emit_modrm(dst, src); |
| 1083 |
emit(imm.value_); |
| 1084 |
} else {
|
| 1085 |
emit(0x69);
|
| 1086 |
emit_modrm(dst, src); |
| 1087 |
emitl(imm.value_); |
| 1088 |
} |
| 1089 |
} |
| 1090 |
|
| 1091 |
|
| 1092 |
void Assembler::incq(Register dst) {
|
| 1093 |
EnsureSpace ensure_space(this);
|
| 1094 |
emit_rex_64(dst); |
| 1095 |
emit(0xFF);
|
| 1096 |
emit_modrm(0x0, dst);
|
| 1097 |
} |
| 1098 |
|
| 1099 |
|
| 1100 |
void Assembler::incq(const Operand& dst) { |
| 1101 |
EnsureSpace ensure_space(this);
|
| 1102 |
emit_rex_64(dst); |
| 1103 |
emit(0xFF);
|
| 1104 |
emit_operand(0, dst);
|
| 1105 |
} |
| 1106 |
|
| 1107 |
|
| 1108 |
void Assembler::incl(const Operand& dst) { |
| 1109 |
EnsureSpace ensure_space(this);
|
| 1110 |
emit_optional_rex_32(dst); |
| 1111 |
emit(0xFF);
|
| 1112 |
emit_operand(0, dst);
|
| 1113 |
} |
| 1114 |
|
| 1115 |
|
| 1116 |
void Assembler::incl(Register dst) {
|
| 1117 |
EnsureSpace ensure_space(this);
|
| 1118 |
emit_optional_rex_32(dst); |
| 1119 |
emit(0xFF);
|
| 1120 |
emit_modrm(0, dst);
|
| 1121 |
} |
| 1122 |
|
| 1123 |
|
| 1124 |
void Assembler::int3() {
|
| 1125 |
EnsureSpace ensure_space(this);
|
| 1126 |
emit(0xCC);
|
| 1127 |
} |
| 1128 |
|
| 1129 |
|
| 1130 |
void Assembler::j(Condition cc, Label* L, Label::Distance distance) {
|
| 1131 |
if (cc == always) {
|
| 1132 |
jmp(L); |
| 1133 |
return;
|
| 1134 |
} else if (cc == never) { |
| 1135 |
return;
|
| 1136 |
} |
| 1137 |
EnsureSpace ensure_space(this);
|
| 1138 |
ASSERT(is_uint4(cc)); |
| 1139 |
if (L->is_bound()) {
|
| 1140 |
const int short_size = 2; |
| 1141 |
const int long_size = 6; |
| 1142 |
int offs = L->pos() - pc_offset();
|
| 1143 |
ASSERT(offs <= 0);
|
| 1144 |
// Determine whether we can use 1-byte offsets for backwards branches,
|
| 1145 |
// which have a max range of 128 bytes.
|
| 1146 |
|
| 1147 |
// We also need to check predictable_code_size() flag here, because on x64,
|
| 1148 |
// when the full code generator recompiles code for debugging, some places
|
| 1149 |
// need to be padded out to a certain size. The debugger is keeping track of
|
| 1150 |
// how often it did this so that it can adjust return addresses on the
|
| 1151 |
// stack, but if the size of jump instructions can also change, that's not
|
| 1152 |
// enough and the calculated offsets would be incorrect.
|
| 1153 |
if (is_int8(offs - short_size) && !predictable_code_size()) {
|
| 1154 |
// 0111 tttn #8-bit disp.
|
| 1155 |
emit(0x70 | cc);
|
| 1156 |
emit((offs - short_size) & 0xFF);
|
| 1157 |
} else {
|
| 1158 |
// 0000 1111 1000 tttn #32-bit disp.
|
| 1159 |
emit(0x0F);
|
| 1160 |
emit(0x80 | cc);
|
| 1161 |
emitl(offs - long_size); |
| 1162 |
} |
| 1163 |
} else if (distance == Label::kNear) { |
| 1164 |
// 0111 tttn #8-bit disp
|
| 1165 |
emit(0x70 | cc);
|
| 1166 |
byte disp = 0x00;
|
| 1167 |
if (L->is_near_linked()) {
|
| 1168 |
int offset = L->near_link_pos() - pc_offset();
|
| 1169 |
ASSERT(is_int8(offset)); |
| 1170 |
disp = static_cast<byte>(offset & 0xFF); |
| 1171 |
} |
| 1172 |
L->link_to(pc_offset(), Label::kNear); |
| 1173 |
emit(disp); |
| 1174 |
} else if (L->is_linked()) { |
| 1175 |
// 0000 1111 1000 tttn #32-bit disp.
|
| 1176 |
emit(0x0F);
|
| 1177 |
emit(0x80 | cc);
|
| 1178 |
emitl(L->pos()); |
| 1179 |
L->link_to(pc_offset() - sizeof(int32_t));
|
| 1180 |
} else {
|
| 1181 |
ASSERT(L->is_unused()); |
| 1182 |
emit(0x0F);
|
| 1183 |
emit(0x80 | cc);
|
| 1184 |
int32_t current = pc_offset(); |
| 1185 |
emitl(current); |
| 1186 |
L->link_to(current); |
| 1187 |
} |
| 1188 |
} |
| 1189 |
|
| 1190 |
|
| 1191 |
void Assembler::j(Condition cc, Address entry, RelocInfo::Mode rmode) {
|
| 1192 |
ASSERT(RelocInfo::IsRuntimeEntry(rmode)); |
| 1193 |
EnsureSpace ensure_space(this);
|
| 1194 |
ASSERT(is_uint4(cc)); |
| 1195 |
emit(0x0F);
|
| 1196 |
emit(0x80 | cc);
|
| 1197 |
emit_runtime_entry(entry, rmode); |
| 1198 |
} |
| 1199 |
|
| 1200 |
|
| 1201 |
void Assembler::j(Condition cc,
|
| 1202 |
Handle<Code> target, |
| 1203 |
RelocInfo::Mode rmode) {
|
| 1204 |
EnsureSpace ensure_space(this);
|
| 1205 |
ASSERT(is_uint4(cc)); |
| 1206 |
// 0000 1111 1000 tttn #32-bit disp.
|
| 1207 |
emit(0x0F);
|
| 1208 |
emit(0x80 | cc);
|
| 1209 |
emit_code_target(target, rmode); |
| 1210 |
} |
| 1211 |
|
| 1212 |
|
| 1213 |
void Assembler::jmp(Label* L, Label::Distance distance) {
|
| 1214 |
EnsureSpace ensure_space(this);
|
| 1215 |
const int short_size = sizeof(int8_t); |
| 1216 |
const int long_size = sizeof(int32_t); |
| 1217 |
if (L->is_bound()) {
|
| 1218 |
int offs = L->pos() - pc_offset() - 1; |
| 1219 |
ASSERT(offs <= 0);
|
| 1220 |
if (is_int8(offs - short_size) && !predictable_code_size()) {
|
| 1221 |
// 1110 1011 #8-bit disp.
|
| 1222 |
emit(0xEB);
|
| 1223 |
emit((offs - short_size) & 0xFF);
|
| 1224 |
} else {
|
| 1225 |
// 1110 1001 #32-bit disp.
|
| 1226 |
emit(0xE9);
|
| 1227 |
emitl(offs - long_size); |
| 1228 |
} |
| 1229 |
} else if (distance == Label::kNear) { |
| 1230 |
emit(0xEB);
|
| 1231 |
byte disp = 0x00;
|
| 1232 |
if (L->is_near_linked()) {
|
| 1233 |
int offset = L->near_link_pos() - pc_offset();
|
| 1234 |
ASSERT(is_int8(offset)); |
| 1235 |
disp = static_cast<byte>(offset & 0xFF); |
| 1236 |
} |
| 1237 |
L->link_to(pc_offset(), Label::kNear); |
| 1238 |
emit(disp); |
| 1239 |
} else if (L->is_linked()) { |
| 1240 |
// 1110 1001 #32-bit disp.
|
| 1241 |
emit(0xE9);
|
| 1242 |
emitl(L->pos()); |
| 1243 |
L->link_to(pc_offset() - long_size); |
| 1244 |
} else {
|
| 1245 |
// 1110 1001 #32-bit disp.
|
| 1246 |
ASSERT(L->is_unused()); |
| 1247 |
emit(0xE9);
|
| 1248 |
int32_t current = pc_offset(); |
| 1249 |
emitl(current); |
| 1250 |
L->link_to(current); |
| 1251 |
} |
| 1252 |
} |
| 1253 |
|
| 1254 |
|
| 1255 |
void Assembler::jmp(Handle<Code> target, RelocInfo::Mode rmode) {
|
| 1256 |
EnsureSpace ensure_space(this);
|
| 1257 |
// 1110 1001 #32-bit disp.
|
| 1258 |
emit(0xE9);
|
| 1259 |
emit_code_target(target, rmode); |
| 1260 |
} |
| 1261 |
|
| 1262 |
|
| 1263 |
void Assembler::jmp(Address entry, RelocInfo::Mode rmode) {
|
| 1264 |
ASSERT(RelocInfo::IsRuntimeEntry(rmode)); |
| 1265 |
EnsureSpace ensure_space(this);
|
| 1266 |
ASSERT(RelocInfo::IsRuntimeEntry(rmode)); |
| 1267 |
emit(0xE9);
|
| 1268 |
emit_runtime_entry(entry, rmode); |
| 1269 |
} |
| 1270 |
|
| 1271 |
|
| 1272 |
void Assembler::jmp(Register target) {
|
| 1273 |
EnsureSpace ensure_space(this);
|
| 1274 |
// Opcode FF/4 r64.
|
| 1275 |
emit_optional_rex_32(target); |
| 1276 |
emit(0xFF);
|
| 1277 |
emit_modrm(0x4, target);
|
| 1278 |
} |
| 1279 |
|
| 1280 |
|
| 1281 |
void Assembler::jmp(const Operand& src) { |
| 1282 |
EnsureSpace ensure_space(this);
|
| 1283 |
// Opcode FF/4 m64.
|
| 1284 |
emit_optional_rex_32(src); |
| 1285 |
emit(0xFF);
|
| 1286 |
emit_operand(0x4, src);
|
| 1287 |
} |
| 1288 |
|
| 1289 |
|
| 1290 |
void Assembler::lea(Register dst, const Operand& src) { |
| 1291 |
EnsureSpace ensure_space(this);
|
| 1292 |
emit_rex_64(dst, src); |
| 1293 |
emit(0x8D);
|
| 1294 |
emit_operand(dst, src); |
| 1295 |
} |
| 1296 |
|
| 1297 |
|
| 1298 |
void Assembler::leal(Register dst, const Operand& src) { |
| 1299 |
EnsureSpace ensure_space(this);
|
| 1300 |
emit_optional_rex_32(dst, src); |
| 1301 |
emit(0x8D);
|
| 1302 |
emit_operand(dst, src); |
| 1303 |
} |
| 1304 |
|
| 1305 |
|
| 1306 |
void Assembler::load_rax(void* value, RelocInfo::Mode mode) { |
| 1307 |
EnsureSpace ensure_space(this);
|
| 1308 |
emit(0x48); // REX.W |
| 1309 |
emit(0xA1);
|
| 1310 |
emitp(value, mode); |
| 1311 |
} |
| 1312 |
|
| 1313 |
|
| 1314 |
void Assembler::load_rax(ExternalReference ref) {
|
| 1315 |
load_rax(ref.address(), RelocInfo::EXTERNAL_REFERENCE); |
| 1316 |
} |
| 1317 |
|
| 1318 |
|
| 1319 |
void Assembler::leave() {
|
| 1320 |
EnsureSpace ensure_space(this);
|
| 1321 |
emit(0xC9);
|
| 1322 |
} |
| 1323 |
|
| 1324 |
|
| 1325 |
void Assembler::movb(Register dst, const Operand& src) { |
| 1326 |
EnsureSpace ensure_space(this);
|
| 1327 |
if (!dst.is_byte_register()) {
|
| 1328 |
// Register is not one of al, bl, cl, dl. Its encoding needs REX.
|
| 1329 |
emit_rex_32(dst, src); |
| 1330 |
} else {
|
| 1331 |
emit_optional_rex_32(dst, src); |
| 1332 |
} |
| 1333 |
emit(0x8A);
|
| 1334 |
emit_operand(dst, src); |
| 1335 |
} |
| 1336 |
|
| 1337 |
|
| 1338 |
void Assembler::movb(Register dst, Immediate imm) {
|
| 1339 |
EnsureSpace ensure_space(this);
|
| 1340 |
if (!dst.is_byte_register()) {
|
| 1341 |
emit_rex_32(dst); |
| 1342 |
} |
| 1343 |
emit(0xB0 + dst.low_bits());
|
| 1344 |
emit(imm.value_); |
| 1345 |
} |
| 1346 |
|
| 1347 |
|
| 1348 |
void Assembler::movb(const Operand& dst, Register src) { |
| 1349 |
EnsureSpace ensure_space(this);
|
| 1350 |
if (!src.is_byte_register()) {
|
| 1351 |
emit_rex_32(src, dst); |
| 1352 |
} else {
|
| 1353 |
emit_optional_rex_32(src, dst); |
| 1354 |
} |
| 1355 |
emit(0x88);
|
| 1356 |
emit_operand(src, dst); |
| 1357 |
} |
| 1358 |
|
| 1359 |
|
| 1360 |
void Assembler::movw(const Operand& dst, Register src) { |
| 1361 |
EnsureSpace ensure_space(this);
|
| 1362 |
emit(0x66);
|
| 1363 |
emit_optional_rex_32(src, dst); |
| 1364 |
emit(0x89);
|
| 1365 |
emit_operand(src, dst); |
| 1366 |
} |
| 1367 |
|
| 1368 |
|
| 1369 |
void Assembler::movl(Register dst, const Operand& src) { |
| 1370 |
EnsureSpace ensure_space(this);
|
| 1371 |
emit_optional_rex_32(dst, src); |
| 1372 |
emit(0x8B);
|
| 1373 |
emit_operand(dst, src); |
| 1374 |
} |
| 1375 |
|
| 1376 |
|
| 1377 |
void Assembler::movl(Register dst, Register src) {
|
| 1378 |
EnsureSpace ensure_space(this);
|
| 1379 |
if (src.low_bits() == 4) { |
| 1380 |
emit_optional_rex_32(src, dst); |
| 1381 |
emit(0x89);
|
| 1382 |
emit_modrm(src, dst); |
| 1383 |
} else {
|
| 1384 |
emit_optional_rex_32(dst, src); |
| 1385 |
emit(0x8B);
|
| 1386 |
emit_modrm(dst, src); |
| 1387 |
} |
| 1388 |
} |
| 1389 |
|
| 1390 |
|
| 1391 |
void Assembler::movl(const Operand& dst, Register src) { |
| 1392 |
EnsureSpace ensure_space(this);
|
| 1393 |
emit_optional_rex_32(src, dst); |
| 1394 |
emit(0x89);
|
| 1395 |
emit_operand(src, dst); |
| 1396 |
} |
| 1397 |
|
| 1398 |
|
| 1399 |
void Assembler::movl(const Operand& dst, Immediate value) { |
| 1400 |
EnsureSpace ensure_space(this);
|
| 1401 |
emit_optional_rex_32(dst); |
| 1402 |
emit(0xC7);
|
| 1403 |
emit_operand(0x0, dst);
|
| 1404 |
emit(value); |
| 1405 |
} |
| 1406 |
|
| 1407 |
|
| 1408 |
void Assembler::movl(Register dst, Immediate value) {
|
| 1409 |
EnsureSpace ensure_space(this);
|
| 1410 |
emit_optional_rex_32(dst); |
| 1411 |
emit(0xB8 + dst.low_bits());
|
| 1412 |
emit(value); |
| 1413 |
} |
| 1414 |
|
| 1415 |
|
| 1416 |
void Assembler::movq(Register dst, const Operand& src) { |
| 1417 |
EnsureSpace ensure_space(this);
|
| 1418 |
emit_rex_64(dst, src); |
| 1419 |
emit(0x8B);
|
| 1420 |
emit_operand(dst, src); |
| 1421 |
} |
| 1422 |
|
| 1423 |
|
| 1424 |
void Assembler::movq(Register dst, Register src) {
|
| 1425 |
EnsureSpace ensure_space(this);
|
| 1426 |
if (src.low_bits() == 4) { |
| 1427 |
emit_rex_64(src, dst); |
| 1428 |
emit(0x89);
|
| 1429 |
emit_modrm(src, dst); |
| 1430 |
} else {
|
| 1431 |
emit_rex_64(dst, src); |
| 1432 |
emit(0x8B);
|
| 1433 |
emit_modrm(dst, src); |
| 1434 |
} |
| 1435 |
} |
| 1436 |
|
| 1437 |
|
| 1438 |
void Assembler::movq(Register dst, Immediate value) {
|
| 1439 |
EnsureSpace ensure_space(this);
|
| 1440 |
emit_rex_64(dst); |
| 1441 |
emit(0xC7);
|
| 1442 |
emit_modrm(0x0, dst);
|
| 1443 |
emit(value); // Only 32-bit immediates are possible, not 8-bit immediates.
|
| 1444 |
} |
| 1445 |
|
| 1446 |
|
| 1447 |
void Assembler::movq(const Operand& dst, Register src) { |
| 1448 |
EnsureSpace ensure_space(this);
|
| 1449 |
emit_rex_64(src, dst); |
| 1450 |
emit(0x89);
|
| 1451 |
emit_operand(src, dst); |
| 1452 |
} |
| 1453 |
|
| 1454 |
|
| 1455 |
void Assembler::movq(Register dst, void* value, RelocInfo::Mode rmode) { |
| 1456 |
// This method must not be used with heap object references. The stored
|
| 1457 |
// address is not GC safe. Use the handle version instead.
|
| 1458 |
ASSERT(rmode > RelocInfo::LAST_GCED_ENUM); |
| 1459 |
EnsureSpace ensure_space(this);
|
| 1460 |
emit_rex_64(dst); |
| 1461 |
emit(0xB8 | dst.low_bits());
|
| 1462 |
emitp(value, rmode); |
| 1463 |
} |
| 1464 |
|
| 1465 |
|
| 1466 |
void Assembler::movq(Register dst, int64_t value, RelocInfo::Mode rmode) {
|
| 1467 |
// Non-relocatable values might not need a 64-bit representation.
|
| 1468 |
ASSERT(RelocInfo::IsNone(rmode)); |
| 1469 |
if (is_uint32(value)) {
|
| 1470 |
movl(dst, Immediate(static_cast<int32_t>(value)));
|
| 1471 |
} else if (is_int32(value)) { |
| 1472 |
movq(dst, Immediate(static_cast<int32_t>(value)));
|
| 1473 |
} else {
|
| 1474 |
// Value cannot be represented by 32 bits, so do a full 64 bit immediate
|
| 1475 |
// value.
|
| 1476 |
EnsureSpace ensure_space(this);
|
| 1477 |
emit_rex_64(dst); |
| 1478 |
emit(0xB8 | dst.low_bits());
|
| 1479 |
emitq(value); |
| 1480 |
} |
| 1481 |
} |
| 1482 |
|
| 1483 |
|
| 1484 |
void Assembler::movq(Register dst, ExternalReference ref) {
|
| 1485 |
Address value = reinterpret_cast<Address>(ref.address());
|
| 1486 |
movq(dst, value, RelocInfo::EXTERNAL_REFERENCE); |
| 1487 |
} |
| 1488 |
|
| 1489 |
|
| 1490 |
void Assembler::movq(const Operand& dst, Immediate value) { |
| 1491 |
EnsureSpace ensure_space(this);
|
| 1492 |
emit_rex_64(dst); |
| 1493 |
emit(0xC7);
|
| 1494 |
emit_operand(0, dst);
|
| 1495 |
emit(value); |
| 1496 |
} |
| 1497 |
|
| 1498 |
|
| 1499 |
// Loads the ip-relative location of the src label into the target location
|
| 1500 |
// (as a 32-bit offset sign extended to 64-bit).
|
| 1501 |
void Assembler::movl(const Operand& dst, Label* src) { |
| 1502 |
EnsureSpace ensure_space(this);
|
| 1503 |
emit_optional_rex_32(dst); |
| 1504 |
emit(0xC7);
|
| 1505 |
emit_operand(0, dst);
|
| 1506 |
if (src->is_bound()) {
|
| 1507 |
int offset = src->pos() - pc_offset() - sizeof(int32_t); |
| 1508 |
ASSERT(offset <= 0);
|
| 1509 |
emitl(offset); |
| 1510 |
} else if (src->is_linked()) { |
| 1511 |
emitl(src->pos()); |
| 1512 |
src->link_to(pc_offset() - sizeof(int32_t));
|
| 1513 |
} else {
|
| 1514 |
ASSERT(src->is_unused()); |
| 1515 |
int32_t current = pc_offset(); |
| 1516 |
emitl(current); |
| 1517 |
src->link_to(current); |
| 1518 |
} |
| 1519 |
} |
| 1520 |
|
| 1521 |
|
| 1522 |
void Assembler::movq(Register dst, Handle<Object> value, RelocInfo::Mode mode) {
|
| 1523 |
AllowDeferredHandleDereference using_raw_address; |
| 1524 |
// If there is no relocation info, emit the value of the handle efficiently
|
| 1525 |
// (possibly using less that 8 bytes for the value).
|
| 1526 |
if (RelocInfo::IsNone(mode)) {
|
| 1527 |
// There is no possible reason to store a heap pointer without relocation
|
| 1528 |
// info, so it must be a smi.
|
| 1529 |
ASSERT(value->IsSmi()); |
| 1530 |
movq(dst, reinterpret_cast<int64_t>(*value), RelocInfo::NONE64);
|
| 1531 |
} else {
|
| 1532 |
EnsureSpace ensure_space(this);
|
| 1533 |
ASSERT(value->IsHeapObject()); |
| 1534 |
ASSERT(!isolate()->heap()->InNewSpace(*value)); |
| 1535 |
emit_rex_64(dst); |
| 1536 |
emit(0xB8 | dst.low_bits());
|
| 1537 |
emitp(value.location(), mode); |
| 1538 |
} |
| 1539 |
} |
| 1540 |
|
| 1541 |
|
| 1542 |
void Assembler::movsxbq(Register dst, const Operand& src) { |
| 1543 |
EnsureSpace ensure_space(this);
|
| 1544 |
emit_rex_64(dst, src); |
| 1545 |
emit(0x0F);
|
| 1546 |
emit(0xBE);
|
| 1547 |
emit_operand(dst, src); |
| 1548 |
} |
| 1549 |
|
| 1550 |
|
| 1551 |
void Assembler::movsxwq(Register dst, const Operand& src) { |
| 1552 |
EnsureSpace ensure_space(this);
|
| 1553 |
emit_rex_64(dst, src); |
| 1554 |
emit(0x0F);
|
| 1555 |
emit(0xBF);
|
| 1556 |
emit_operand(dst, src); |
| 1557 |
} |
| 1558 |
|
| 1559 |
|
| 1560 |
void Assembler::movsxlq(Register dst, Register src) {
|
| 1561 |
EnsureSpace ensure_space(this);
|
| 1562 |
emit_rex_64(dst, src); |
| 1563 |
emit(0x63);
|
| 1564 |
emit_modrm(dst, src); |
| 1565 |
} |
| 1566 |
|
| 1567 |
|
| 1568 |
void Assembler::movsxlq(Register dst, const Operand& src) { |
| 1569 |
EnsureSpace ensure_space(this);
|
| 1570 |
emit_rex_64(dst, src); |
| 1571 |
emit(0x63);
|
| 1572 |
emit_operand(dst, src); |
| 1573 |
} |
| 1574 |
|
| 1575 |
|
| 1576 |
void Assembler::movzxbq(Register dst, const Operand& src) { |
| 1577 |
EnsureSpace ensure_space(this);
|
| 1578 |
// 32 bit operations zero the top 32 bits of 64 bit registers. Therefore
|
| 1579 |
// there is no need to make this a 64 bit operation.
|
| 1580 |
emit_optional_rex_32(dst, src); |
| 1581 |
emit(0x0F);
|
| 1582 |
emit(0xB6);
|
| 1583 |
emit_operand(dst, src); |
| 1584 |
} |
| 1585 |
|
| 1586 |
|
| 1587 |
void Assembler::movzxbl(Register dst, const Operand& src) { |
| 1588 |
EnsureSpace ensure_space(this);
|
| 1589 |
emit_optional_rex_32(dst, src); |
| 1590 |
emit(0x0F);
|
| 1591 |
emit(0xB6);
|
| 1592 |
emit_operand(dst, src); |
| 1593 |
} |
| 1594 |
|
| 1595 |
|
| 1596 |
void Assembler::movzxwq(Register dst, const Operand& src) { |
| 1597 |
EnsureSpace ensure_space(this);
|
| 1598 |
emit_optional_rex_32(dst, src); |
| 1599 |
emit(0x0F);
|
| 1600 |
emit(0xB7);
|
| 1601 |
emit_operand(dst, src); |
| 1602 |
} |
| 1603 |
|
| 1604 |
|
| 1605 |
void Assembler::movzxwl(Register dst, const Operand& src) { |
| 1606 |
EnsureSpace ensure_space(this);
|
| 1607 |
emit_optional_rex_32(dst, src); |
| 1608 |
emit(0x0F);
|
| 1609 |
emit(0xB7);
|
| 1610 |
emit_operand(dst, src); |
| 1611 |
} |
| 1612 |
|
| 1613 |
|
| 1614 |
void Assembler::movzxwl(Register dst, Register src) {
|
| 1615 |
EnsureSpace ensure_space(this);
|
| 1616 |
emit_optional_rex_32(dst, src); |
| 1617 |
emit(0x0F);
|
| 1618 |
emit(0xB7);
|
| 1619 |
emit_modrm(dst, src); |
| 1620 |
} |
| 1621 |
|
| 1622 |
|
| 1623 |
void Assembler::repmovsb() {
|
| 1624 |
EnsureSpace ensure_space(this);
|
| 1625 |
emit(0xF3);
|
| 1626 |
emit(0xA4);
|
| 1627 |
} |
| 1628 |
|
| 1629 |
|
| 1630 |
void Assembler::repmovsw() {
|
| 1631 |
EnsureSpace ensure_space(this);
|
| 1632 |
emit(0x66); // Operand size override. |
| 1633 |
emit(0xF3);
|
| 1634 |
emit(0xA4);
|
| 1635 |
} |
| 1636 |
|
| 1637 |
|
| 1638 |
void Assembler::repmovsl() {
|
| 1639 |
EnsureSpace ensure_space(this);
|
| 1640 |
emit(0xF3);
|
| 1641 |
emit(0xA5);
|
| 1642 |
} |
| 1643 |
|
| 1644 |
|
| 1645 |
void Assembler::repmovsq() {
|
| 1646 |
EnsureSpace ensure_space(this);
|
| 1647 |
emit(0xF3);
|
| 1648 |
emit_rex_64(); |
| 1649 |
emit(0xA5);
|
| 1650 |
} |
| 1651 |
|
| 1652 |
|
| 1653 |
void Assembler::mul(Register src) {
|
| 1654 |
EnsureSpace ensure_space(this);
|
| 1655 |
emit_rex_64(src); |
| 1656 |
emit(0xF7);
|
| 1657 |
emit_modrm(0x4, src);
|
| 1658 |
} |
| 1659 |
|
| 1660 |
|
| 1661 |
void Assembler::neg(Register dst) {
|
| 1662 |
EnsureSpace ensure_space(this);
|
| 1663 |
emit_rex_64(dst); |
| 1664 |
emit(0xF7);
|
| 1665 |
emit_modrm(0x3, dst);
|
| 1666 |
} |
| 1667 |
|
| 1668 |
|
| 1669 |
void Assembler::negl(Register dst) {
|
| 1670 |
EnsureSpace ensure_space(this);
|
| 1671 |
emit_optional_rex_32(dst); |
| 1672 |
emit(0xF7);
|
| 1673 |
emit_modrm(0x3, dst);
|
| 1674 |
} |
| 1675 |
|
| 1676 |
|
| 1677 |
void Assembler::neg(const Operand& dst) { |
| 1678 |
EnsureSpace ensure_space(this);
|
| 1679 |
emit_rex_64(dst); |
| 1680 |
emit(0xF7);
|
| 1681 |
emit_operand(3, dst);
|
| 1682 |
} |
| 1683 |
|
| 1684 |
|
| 1685 |
void Assembler::nop() {
|
| 1686 |
EnsureSpace ensure_space(this);
|
| 1687 |
emit(0x90);
|
| 1688 |
} |
| 1689 |
|
| 1690 |
|
| 1691 |
void Assembler::not_(Register dst) {
|
| 1692 |
EnsureSpace ensure_space(this);
|
| 1693 |
emit_rex_64(dst); |
| 1694 |
emit(0xF7);
|
| 1695 |
emit_modrm(0x2, dst);
|
| 1696 |
} |
| 1697 |
|
| 1698 |
|
| 1699 |
void Assembler::not_(const Operand& dst) { |
| 1700 |
EnsureSpace ensure_space(this);
|
| 1701 |
emit_rex_64(dst); |
| 1702 |
emit(0xF7);
|
| 1703 |
emit_operand(2, dst);
|
| 1704 |
} |
| 1705 |
|
| 1706 |
|
| 1707 |
void Assembler::notl(Register dst) {
|
| 1708 |
EnsureSpace ensure_space(this);
|
| 1709 |
emit_optional_rex_32(dst); |
| 1710 |
emit(0xF7);
|
| 1711 |
emit_modrm(0x2, dst);
|
| 1712 |
} |
| 1713 |
|
| 1714 |
|
| 1715 |
void Assembler::Nop(int n) { |
| 1716 |
// The recommended muti-byte sequences of NOP instructions from the Intel 64
|
| 1717 |
// and IA-32 Architectures Software Developer's Manual.
|
| 1718 |
//
|
| 1719 |
// Length Assembly Byte Sequence
|
| 1720 |
// 2 bytes 66 NOP 66 90H
|
| 1721 |
// 3 bytes NOP DWORD ptr [EAX] 0F 1F 00H
|
| 1722 |
// 4 bytes NOP DWORD ptr [EAX + 00H] 0F 1F 40 00H
|
| 1723 |
// 5 bytes NOP DWORD ptr [EAX + EAX*1 + 00H] 0F 1F 44 00 00H
|
| 1724 |
// 6 bytes 66 NOP DWORD ptr [EAX + EAX*1 + 00H] 66 0F 1F 44 00 00H
|
| 1725 |
// 7 bytes NOP DWORD ptr [EAX + 00000000H] 0F 1F 80 00 00 00 00H
|
| 1726 |
// 8 bytes NOP DWORD ptr [EAX + EAX*1 + 00000000H] 0F 1F 84 00 00 00 00 00H
|
| 1727 |
// 9 bytes 66 NOP DWORD ptr [EAX + EAX*1 + 66 0F 1F 84 00 00 00 00
|
| 1728 |
// 00000000H] 00H
|
| 1729 |
|
| 1730 |
EnsureSpace ensure_space(this);
|
| 1731 |
while (n > 0) { |
| 1732 |
switch (n) {
|
| 1733 |
case 2: |
| 1734 |
emit(0x66);
|
| 1735 |
case 1: |
| 1736 |
emit(0x90);
|
| 1737 |
return;
|
| 1738 |
case 3: |
| 1739 |
emit(0x0f);
|
| 1740 |
emit(0x1f);
|
| 1741 |
emit(0x00);
|
| 1742 |
return;
|
| 1743 |
case 4: |
| 1744 |
emit(0x0f);
|
| 1745 |
emit(0x1f);
|
| 1746 |
emit(0x40);
|
| 1747 |
emit(0x00);
|
| 1748 |
return;
|
| 1749 |
case 6: |
| 1750 |
emit(0x66);
|
| 1751 |
case 5: |
| 1752 |
emit(0x0f);
|
| 1753 |
emit(0x1f);
|
| 1754 |
emit(0x44);
|
| 1755 |
emit(0x00);
|
| 1756 |
emit(0x00);
|
| 1757 |
return;
|
| 1758 |
case 7: |
| 1759 |
emit(0x0f);
|
| 1760 |
emit(0x1f);
|
| 1761 |
emit(0x80);
|
| 1762 |
emit(0x00);
|
| 1763 |
emit(0x00);
|
| 1764 |
emit(0x00);
|
| 1765 |
emit(0x00);
|
| 1766 |
return;
|
| 1767 |
default:
|
| 1768 |
case 11: |
| 1769 |
emit(0x66);
|
| 1770 |
n--; |
| 1771 |
case 10: |
| 1772 |
emit(0x66);
|
| 1773 |
n--; |
| 1774 |
case 9: |
| 1775 |
emit(0x66);
|
| 1776 |
n--; |
| 1777 |
case 8: |
| 1778 |
emit(0x0f);
|
| 1779 |
emit(0x1f);
|
| 1780 |
emit(0x84);
|
| 1781 |
emit(0x00);
|
| 1782 |
emit(0x00);
|
| 1783 |
emit(0x00);
|
| 1784 |
emit(0x00);
|
| 1785 |
emit(0x00);
|
| 1786 |
n -= 8;
|
| 1787 |
} |
| 1788 |
} |
| 1789 |
} |
| 1790 |
|
| 1791 |
|
| 1792 |
void Assembler::pop(Register dst) {
|
| 1793 |
EnsureSpace ensure_space(this);
|
| 1794 |
emit_optional_rex_32(dst); |
| 1795 |
emit(0x58 | dst.low_bits());
|
| 1796 |
} |
| 1797 |
|
| 1798 |
|
| 1799 |
void Assembler::pop(const Operand& dst) { |
| 1800 |
EnsureSpace ensure_space(this);
|
| 1801 |
emit_optional_rex_32(dst); |
| 1802 |
emit(0x8F);
|
| 1803 |
emit_operand(0, dst);
|
| 1804 |
} |
| 1805 |
|
| 1806 |
|
| 1807 |
void Assembler::popfq() {
|
| 1808 |
EnsureSpace ensure_space(this);
|
| 1809 |
emit(0x9D);
|
| 1810 |
} |
| 1811 |
|
| 1812 |
|
| 1813 |
void Assembler::push(Register src) {
|
| 1814 |
EnsureSpace ensure_space(this);
|
| 1815 |
emit_optional_rex_32(src); |
| 1816 |
emit(0x50 | src.low_bits());
|
| 1817 |
} |
| 1818 |
|
| 1819 |
|
| 1820 |
void Assembler::push(const Operand& src) { |
| 1821 |
EnsureSpace ensure_space(this);
|
| 1822 |
emit_optional_rex_32(src); |
| 1823 |
emit(0xFF);
|
| 1824 |
emit_operand(6, src);
|
| 1825 |
} |
| 1826 |
|
| 1827 |
|
| 1828 |
void Assembler::push(Immediate value) {
|
| 1829 |
EnsureSpace ensure_space(this);
|
| 1830 |
if (is_int8(value.value_)) {
|
| 1831 |
emit(0x6A);
|
| 1832 |
emit(value.value_); // Emit low byte of value.
|
| 1833 |
} else {
|
| 1834 |
emit(0x68);
|
| 1835 |
emitl(value.value_); |
| 1836 |
} |
| 1837 |
} |
| 1838 |
|
| 1839 |
|
| 1840 |
void Assembler::push_imm32(int32_t imm32) {
|
| 1841 |
EnsureSpace ensure_space(this);
|
| 1842 |
emit(0x68);
|
| 1843 |
emitl(imm32); |
| 1844 |
} |
| 1845 |
|
| 1846 |
|
| 1847 |
void Assembler::pushfq() {
|
| 1848 |
EnsureSpace ensure_space(this);
|
| 1849 |
emit(0x9C);
|
| 1850 |
} |
| 1851 |
|
| 1852 |
|
| 1853 |
void Assembler::ret(int imm16) { |
| 1854 |
EnsureSpace ensure_space(this);
|
| 1855 |
ASSERT(is_uint16(imm16)); |
| 1856 |
if (imm16 == 0) { |
| 1857 |
emit(0xC3);
|
| 1858 |
} else {
|
| 1859 |
emit(0xC2);
|
| 1860 |
emit(imm16 & 0xFF);
|
| 1861 |
emit((imm16 >> 8) & 0xFF); |
| 1862 |
} |
| 1863 |
} |
| 1864 |
|
| 1865 |
|
| 1866 |
void Assembler::setcc(Condition cc, Register reg) {
|
| 1867 |
if (cc > last_condition) {
|
| 1868 |
movb(reg, Immediate(cc == always ? 1 : 0)); |
| 1869 |
return;
|
| 1870 |
} |
| 1871 |
EnsureSpace ensure_space(this);
|
| 1872 |
ASSERT(is_uint4(cc)); |
| 1873 |
if (!reg.is_byte_register()) { // Use x64 byte registers, where different. |
| 1874 |
emit_rex_32(reg); |
| 1875 |
} |
| 1876 |
emit(0x0F);
|
| 1877 |
emit(0x90 | cc);
|
| 1878 |
emit_modrm(0x0, reg);
|
| 1879 |
} |
| 1880 |
|
| 1881 |
|
| 1882 |
void Assembler::shld(Register dst, Register src) {
|
| 1883 |
EnsureSpace ensure_space(this);
|
| 1884 |
emit_rex_64(src, dst); |
| 1885 |
emit(0x0F);
|
| 1886 |
emit(0xA5);
|
| 1887 |
emit_modrm(src, dst); |
| 1888 |
} |
| 1889 |
|
| 1890 |
|
| 1891 |
void Assembler::shrd(Register dst, Register src) {
|
| 1892 |
EnsureSpace ensure_space(this);
|
| 1893 |
emit_rex_64(src, dst); |
| 1894 |
emit(0x0F);
|
| 1895 |
emit(0xAD);
|
| 1896 |
emit_modrm(src, dst); |
| 1897 |
} |
| 1898 |
|
| 1899 |
|
| 1900 |
void Assembler::xchgq(Register dst, Register src) {
|
| 1901 |
EnsureSpace ensure_space(this);
|
| 1902 |
if (src.is(rax) || dst.is(rax)) { // Single-byte encoding |
| 1903 |
Register other = src.is(rax) ? dst : src; |
| 1904 |
emit_rex_64(other); |
| 1905 |
emit(0x90 | other.low_bits());
|
| 1906 |
} else if (dst.low_bits() == 4) { |
| 1907 |
emit_rex_64(dst, src); |
| 1908 |
emit(0x87);
|
| 1909 |
emit_modrm(dst, src); |
| 1910 |
} else {
|
| 1911 |
emit_rex_64(src, dst); |
| 1912 |
emit(0x87);
|
| 1913 |
emit_modrm(src, dst); |
| 1914 |
} |
| 1915 |
} |
| 1916 |
|
| 1917 |
|
| 1918 |
void Assembler::xchgl(Register dst, Register src) {
|
| 1919 |
EnsureSpace ensure_space(this);
|
| 1920 |
if (src.is(rax) || dst.is(rax)) { // Single-byte encoding |
| 1921 |
Register other = src.is(rax) ? dst : src; |
| 1922 |
emit_optional_rex_32(other); |
| 1923 |
emit(0x90 | other.low_bits());
|
| 1924 |
} else if (dst.low_bits() == 4) { |
| 1925 |
emit_optional_rex_32(dst, src); |
| 1926 |
emit(0x87);
|
| 1927 |
emit_modrm(dst, src); |
| 1928 |
} else {
|
| 1929 |
emit_optional_rex_32(src, dst); |
| 1930 |
emit(0x87);
|
| 1931 |
emit_modrm(src, dst); |
| 1932 |
} |
| 1933 |
} |
| 1934 |
|
| 1935 |
|
| 1936 |
void Assembler::store_rax(void* dst, RelocInfo::Mode mode) { |
| 1937 |
EnsureSpace ensure_space(this);
|
| 1938 |
emit(0x48); // REX.W |
| 1939 |
emit(0xA3);
|
| 1940 |
emitp(dst, mode); |
| 1941 |
} |
| 1942 |
|
| 1943 |
|
| 1944 |
void Assembler::store_rax(ExternalReference ref) {
|
| 1945 |
store_rax(ref.address(), RelocInfo::EXTERNAL_REFERENCE); |
| 1946 |
} |
| 1947 |
|
| 1948 |
|
| 1949 |
void Assembler::testb(Register dst, Register src) {
|
| 1950 |
EnsureSpace ensure_space(this);
|
| 1951 |
if (src.low_bits() == 4) { |
| 1952 |
emit_rex_32(src, dst); |
| 1953 |
emit(0x84);
|
| 1954 |
emit_modrm(src, dst); |
| 1955 |
} else {
|
| 1956 |
if (!dst.is_byte_register() || !src.is_byte_register()) {
|
| 1957 |
// Register is not one of al, bl, cl, dl. Its encoding needs REX.
|
| 1958 |
emit_rex_32(dst, src); |
| 1959 |
} |
| 1960 |
emit(0x84);
|
| 1961 |
emit_modrm(dst, src); |
| 1962 |
} |
| 1963 |
} |
| 1964 |
|
| 1965 |
|
| 1966 |
void Assembler::testb(Register reg, Immediate mask) {
|
| 1967 |
ASSERT(is_int8(mask.value_) || is_uint8(mask.value_)); |
| 1968 |
EnsureSpace ensure_space(this);
|
| 1969 |
if (reg.is(rax)) {
|
| 1970 |
emit(0xA8);
|
| 1971 |
emit(mask.value_); // Low byte emitted.
|
| 1972 |
} else {
|
| 1973 |
if (!reg.is_byte_register()) {
|
| 1974 |
// Register is not one of al, bl, cl, dl. Its encoding needs REX.
|
| 1975 |
emit_rex_32(reg); |
| 1976 |
} |
| 1977 |
emit(0xF6);
|
| 1978 |
emit_modrm(0x0, reg);
|
| 1979 |
emit(mask.value_); // Low byte emitted.
|
| 1980 |
} |
| 1981 |
} |
| 1982 |
|
| 1983 |
|
| 1984 |
void Assembler::testb(const Operand& op, Immediate mask) { |
| 1985 |
ASSERT(is_int8(mask.value_) || is_uint8(mask.value_)); |
| 1986 |
EnsureSpace ensure_space(this);
|
| 1987 |
emit_optional_rex_32(rax, op); |
| 1988 |
emit(0xF6);
|
| 1989 |
emit_operand(rax, op); // Operation code 0
|
| 1990 |
emit(mask.value_); // Low byte emitted.
|
| 1991 |
} |
| 1992 |
|
| 1993 |
|
| 1994 |
void Assembler::testb(const Operand& op, Register reg) { |
| 1995 |
EnsureSpace ensure_space(this);
|
| 1996 |
if (!reg.is_byte_register()) {
|
| 1997 |
// Register is not one of al, bl, cl, dl. Its encoding needs REX.
|
| 1998 |
emit_rex_32(reg, op); |
| 1999 |
} else {
|
| 2000 |
emit_optional_rex_32(reg, op); |
| 2001 |
} |
| 2002 |
emit(0x84);
|
| 2003 |
emit_operand(reg, op); |
| 2004 |
} |
| 2005 |
|
| 2006 |
|
| 2007 |
void Assembler::testl(Register dst, Register src) {
|
| 2008 |
EnsureSpace ensure_space(this);
|
| 2009 |
if (src.low_bits() == 4) { |
| 2010 |
emit_optional_rex_32(src, dst); |
| 2011 |
emit(0x85);
|
| 2012 |
emit_modrm(src, dst); |
| 2013 |
} else {
|
| 2014 |
emit_optional_rex_32(dst, src); |
| 2015 |
emit(0x85);
|
| 2016 |
emit_modrm(dst, src); |
| 2017 |
} |
| 2018 |
} |
| 2019 |
|
| 2020 |
|
| 2021 |
void Assembler::testl(Register reg, Immediate mask) {
|
| 2022 |
// testl with a mask that fits in the low byte is exactly testb.
|
| 2023 |
if (is_uint8(mask.value_)) {
|
| 2024 |
testb(reg, mask); |
| 2025 |
return;
|
| 2026 |
} |
| 2027 |
EnsureSpace ensure_space(this);
|
| 2028 |
if (reg.is(rax)) {
|
| 2029 |
emit(0xA9);
|
| 2030 |
emit(mask); |
| 2031 |
} else {
|
| 2032 |
emit_optional_rex_32(rax, reg); |
| 2033 |
emit(0xF7);
|
| 2034 |
emit_modrm(0x0, reg);
|
| 2035 |
emit(mask); |
| 2036 |
} |
| 2037 |
} |
| 2038 |
|
| 2039 |
|
| 2040 |
void Assembler::testl(const Operand& op, Immediate mask) { |
| 2041 |
// testl with a mask that fits in the low byte is exactly testb.
|
| 2042 |
if (is_uint8(mask.value_)) {
|
| 2043 |
testb(op, mask); |
| 2044 |
return;
|
| 2045 |
} |
| 2046 |
EnsureSpace ensure_space(this);
|
| 2047 |
emit_optional_rex_32(rax, op); |
| 2048 |
emit(0xF7);
|
| 2049 |
emit_operand(rax, op); // Operation code 0
|
| 2050 |
emit(mask); |
| 2051 |
} |
| 2052 |
|
| 2053 |
|
| 2054 |
void Assembler::testl(const Operand& op, Register reg) { |
| 2055 |
EnsureSpace ensure_space(this);
|
| 2056 |
emit_optional_rex_32(reg, op); |
| 2057 |
emit(0x85);
|
| 2058 |
emit_operand(reg, op); |
| 2059 |
} |
| 2060 |
|
| 2061 |
|
| 2062 |
void Assembler::testq(const Operand& op, Register reg) { |
| 2063 |
EnsureSpace ensure_space(this);
|
| 2064 |
emit_rex_64(reg, op); |
| 2065 |
emit(0x85);
|
| 2066 |
emit_operand(reg, op); |
| 2067 |
} |
| 2068 |
|
| 2069 |
|
| 2070 |
void Assembler::testq(Register dst, Register src) {
|
| 2071 |
EnsureSpace ensure_space(this);
|
| 2072 |
if (src.low_bits() == 4) { |
| 2073 |
emit_rex_64(src, dst); |
| 2074 |
emit(0x85);
|
| 2075 |
emit_modrm(src, dst); |
| 2076 |
} else {
|
| 2077 |
emit_rex_64(dst, src); |
| 2078 |
emit(0x85);
|
| 2079 |
emit_modrm(dst, src); |
| 2080 |
} |
| 2081 |
} |
| 2082 |
|
| 2083 |
|
| 2084 |
void Assembler::testq(Register dst, Immediate mask) {
|
| 2085 |
if (is_uint8(mask.value_)) {
|
| 2086 |
testb(dst, mask); |
| 2087 |
return;
|
| 2088 |
} |
| 2089 |
EnsureSpace ensure_space(this);
|
| 2090 |
if (dst.is(rax)) {
|
| 2091 |
emit_rex_64(); |
| 2092 |
emit(0xA9);
|
| 2093 |
emit(mask); |
| 2094 |
} else {
|
| 2095 |
emit_rex_64(dst); |
| 2096 |
emit(0xF7);
|
| 2097 |
emit_modrm(0, dst);
|
| 2098 |
emit(mask); |
| 2099 |
} |
| 2100 |
} |
| 2101 |
|
| 2102 |
|
| 2103 |
// FPU instructions.
|
| 2104 |
|
| 2105 |
|
| 2106 |
void Assembler::fld(int i) { |
| 2107 |
EnsureSpace ensure_space(this);
|
| 2108 |
emit_farith(0xD9, 0xC0, i); |
| 2109 |
} |
| 2110 |
|
| 2111 |
|
| 2112 |
void Assembler::fld1() {
|
| 2113 |
EnsureSpace ensure_space(this);
|
| 2114 |
emit(0xD9);
|
| 2115 |
emit(0xE8);
|
| 2116 |
} |
| 2117 |
|
| 2118 |
|
| 2119 |
void Assembler::fldz() {
|
| 2120 |
EnsureSpace ensure_space(this);
|
| 2121 |
emit(0xD9);
|
| 2122 |
emit(0xEE);
|
| 2123 |
} |
| 2124 |
|
| 2125 |
|
| 2126 |
void Assembler::fldpi() {
|
| 2127 |
EnsureSpace ensure_space(this);
|
| 2128 |
emit(0xD9);
|
| 2129 |
emit(0xEB);
|
| 2130 |
} |
| 2131 |
|
| 2132 |
|
| 2133 |
void Assembler::fldln2() {
|
| 2134 |
EnsureSpace ensure_space(this);
|
| 2135 |
emit(0xD9);
|
| 2136 |
emit(0xED);
|
| 2137 |
} |
| 2138 |
|
| 2139 |
|
| 2140 |
void Assembler::fld_s(const Operand& adr) { |
| 2141 |
EnsureSpace ensure_space(this);
|
| 2142 |
emit_optional_rex_32(adr); |
| 2143 |
emit(0xD9);
|
| 2144 |
emit_operand(0, adr);
|
| 2145 |
} |
| 2146 |
|
| 2147 |
|
| 2148 |
void Assembler::fld_d(const Operand& adr) { |
| 2149 |
EnsureSpace ensure_space(this);
|
| 2150 |
emit_optional_rex_32(adr); |
| 2151 |
emit(0xDD);
|
| 2152 |
emit_operand(0, adr);
|
| 2153 |
} |
| 2154 |
|
| 2155 |
|
| 2156 |
void Assembler::fstp_s(const Operand& adr) { |
| 2157 |
EnsureSpace ensure_space(this);
|
| 2158 |
emit_optional_rex_32(adr); |
| 2159 |
emit(0xD9);
|
| 2160 |
emit_operand(3, adr);
|
| 2161 |
} |
| 2162 |
|
| 2163 |
|
| 2164 |
void Assembler::fstp_d(const Operand& adr) { |
| 2165 |
EnsureSpace ensure_space(this);
|
| 2166 |
emit_optional_rex_32(adr); |
| 2167 |
emit(0xDD);
|
| 2168 |
emit_operand(3, adr);
|
| 2169 |
} |
| 2170 |
|
| 2171 |
|
| 2172 |
void Assembler::fstp(int index) { |
| 2173 |
ASSERT(is_uint3(index)); |
| 2174 |
EnsureSpace ensure_space(this);
|
| 2175 |
emit_farith(0xDD, 0xD8, index); |
| 2176 |
} |
| 2177 |
|
| 2178 |
|
| 2179 |
void Assembler::fild_s(const Operand& adr) { |
| 2180 |
EnsureSpace ensure_space(this);
|
| 2181 |
emit_optional_rex_32(adr); |
| 2182 |
emit(0xDB);
|
| 2183 |
emit_operand(0, adr);
|
| 2184 |
} |
| 2185 |
|
| 2186 |
|
| 2187 |
void Assembler::fild_d(const Operand& adr) { |
| 2188 |
EnsureSpace ensure_space(this);
|
| 2189 |
emit_optional_rex_32(adr); |
| 2190 |
emit(0xDF);
|
| 2191 |
emit_operand(5, adr);
|
| 2192 |
} |
| 2193 |
|
| 2194 |
|
| 2195 |
void Assembler::fistp_s(const Operand& adr) { |
| 2196 |
EnsureSpace ensure_space(this);
|
| 2197 |
emit_optional_rex_32(adr); |
| 2198 |
emit(0xDB);
|
| 2199 |
emit_operand(3, adr);
|
| 2200 |
} |
| 2201 |
|
| 2202 |
|
| 2203 |
void Assembler::fisttp_s(const Operand& adr) { |
| 2204 |
ASSERT(IsEnabled(SSE3)); |
| 2205 |
EnsureSpace ensure_space(this);
|
| 2206 |
emit_optional_rex_32(adr); |
| 2207 |
emit(0xDB);
|
| 2208 |
emit_operand(1, adr);
|
| 2209 |
} |
| 2210 |
|
| 2211 |
|
| 2212 |
void Assembler::fisttp_d(const Operand& adr) { |
| 2213 |
ASSERT(IsEnabled(SSE3)); |
| 2214 |
EnsureSpace ensure_space(this);
|
| 2215 |
emit_optional_rex_32(adr); |
| 2216 |
emit(0xDD);
|
| 2217 |
emit_operand(1, adr);
|
| 2218 |
} |
| 2219 |
|
| 2220 |
|
| 2221 |
void Assembler::fist_s(const Operand& adr) { |
| 2222 |
EnsureSpace ensure_space(this);
|
| 2223 |
emit_optional_rex_32(adr); |
| 2224 |
emit(0xDB);
|
| 2225 |
emit_operand(2, adr);
|
| 2226 |
} |
| 2227 |
|
| 2228 |
|
| 2229 |
void Assembler::fistp_d(const Operand& adr) { |
| 2230 |
EnsureSpace ensure_space(this);
|
| 2231 |
emit_optional_rex_32(adr); |
| 2232 |
emit(0xDF);
|
| 2233 |
emit_operand(7, adr);
|
| 2234 |
} |
| 2235 |
|
| 2236 |
|
| 2237 |
void Assembler::fabs() {
|
| 2238 |
EnsureSpace ensure_space(this);
|
| 2239 |
emit(0xD9);
|
| 2240 |
emit(0xE1);
|
| 2241 |
} |
| 2242 |
|
| 2243 |
|
| 2244 |
void Assembler::fchs() {
|
| 2245 |
EnsureSpace ensure_space(this);
|
| 2246 |
emit(0xD9);
|
| 2247 |
emit(0xE0);
|
| 2248 |
} |
| 2249 |
|
| 2250 |
|
| 2251 |
void Assembler::fcos() {
|
| 2252 |
EnsureSpace ensure_space(this);
|
| 2253 |
emit(0xD9);
|
| 2254 |
emit(0xFF);
|
| 2255 |
} |
| 2256 |
|
| 2257 |
|
| 2258 |
void Assembler::fsin() {
|
| 2259 |
EnsureSpace ensure_space(this);
|
| 2260 |
emit(0xD9);
|
| 2261 |
emit(0xFE);
|
| 2262 |
} |
| 2263 |
|
| 2264 |
|
| 2265 |
void Assembler::fptan() {
|
| 2266 |
EnsureSpace ensure_space(this);
|
| 2267 |
emit(0xD9);
|
| 2268 |
emit(0xF2);
|
| 2269 |
} |
| 2270 |
|
| 2271 |
|
| 2272 |
void Assembler::fyl2x() {
|
| 2273 |
EnsureSpace ensure_space(this);
|
| 2274 |
emit(0xD9);
|
| 2275 |
emit(0xF1);
|
| 2276 |
} |
| 2277 |
|
| 2278 |
|
| 2279 |
void Assembler::f2xm1() {
|
| 2280 |
EnsureSpace ensure_space(this);
|
| 2281 |
emit(0xD9);
|
| 2282 |
emit(0xF0);
|
| 2283 |
} |
| 2284 |
|
| 2285 |
|
| 2286 |
void Assembler::fscale() {
|
| 2287 |
EnsureSpace ensure_space(this);
|
| 2288 |
emit(0xD9);
|
| 2289 |
emit(0xFD);
|
| 2290 |
} |
| 2291 |
|
| 2292 |
|
| 2293 |
void Assembler::fninit() {
|
| 2294 |
EnsureSpace ensure_space(this);
|
| 2295 |
emit(0xDB);
|
| 2296 |
emit(0xE3);
|
| 2297 |
} |
| 2298 |
|
| 2299 |
|
| 2300 |
void Assembler::fadd(int i) { |
| 2301 |
EnsureSpace ensure_space(this);
|
| 2302 |
emit_farith(0xDC, 0xC0, i); |
| 2303 |
} |
| 2304 |
|
| 2305 |
|
| 2306 |
void Assembler::fsub(int i) { |
| 2307 |
EnsureSpace ensure_space(this);
|
| 2308 |
emit_farith(0xDC, 0xE8, i); |
| 2309 |
} |
| 2310 |
|
| 2311 |
|
| 2312 |
void Assembler::fisub_s(const Operand& adr) { |
| 2313 |
EnsureSpace ensure_space(this);
|
| 2314 |
emit_optional_rex_32(adr); |
| 2315 |
emit(0xDA);
|
| 2316 |
emit_operand(4, adr);
|
| 2317 |
} |
| 2318 |
|
| 2319 |
|
| 2320 |
void Assembler::fmul(int i) { |
| 2321 |
EnsureSpace ensure_space(this);
|
| 2322 |
emit_farith(0xDC, 0xC8, i); |
| 2323 |
} |
| 2324 |
|
| 2325 |
|
| 2326 |
void Assembler::fdiv(int i) { |
| 2327 |
EnsureSpace ensure_space(this);
|
| 2328 |
emit_farith(0xDC, 0xF8, i); |
| 2329 |
} |
| 2330 |
|
| 2331 |
|
| 2332 |
void Assembler::faddp(int i) { |
| 2333 |
EnsureSpace ensure_space(this);
|
| 2334 |
emit_farith(0xDE, 0xC0, i); |
| 2335 |
} |
| 2336 |
|
| 2337 |
|
| 2338 |
void Assembler::fsubp(int i) { |
| 2339 |
EnsureSpace ensure_space(this);
|
| 2340 |
emit_farith(0xDE, 0xE8, i); |
| 2341 |
} |
| 2342 |
|
| 2343 |
|
| 2344 |
void Assembler::fsubrp(int i) { |
| 2345 |
EnsureSpace ensure_space(this);
|
| 2346 |
emit_farith(0xDE, 0xE0, i); |
| 2347 |
} |
| 2348 |
|
| 2349 |
|
| 2350 |
void Assembler::fmulp(int i) { |
| 2351 |
EnsureSpace ensure_space(this);
|
| 2352 |
emit_farith(0xDE, 0xC8, i); |
| 2353 |
} |
| 2354 |
|
| 2355 |
|
| 2356 |
void Assembler::fdivp(int i) { |
| 2357 |
EnsureSpace ensure_space(this);
|
| 2358 |
emit_farith(0xDE, 0xF8, i); |
| 2359 |
} |
| 2360 |
|
| 2361 |
|
| 2362 |
void Assembler::fprem() {
|
| 2363 |
EnsureSpace ensure_space(this);
|
| 2364 |
emit(0xD9);
|
| 2365 |
emit(0xF8);
|
| 2366 |
} |
| 2367 |
|
| 2368 |
|
| 2369 |
void Assembler::fprem1() {
|
| 2370 |
EnsureSpace ensure_space(this);
|
| 2371 |
emit(0xD9);
|
| 2372 |
emit(0xF5);
|
| 2373 |
} |
| 2374 |
|
| 2375 |
|
| 2376 |
void Assembler::fxch(int i) { |
| 2377 |
EnsureSpace ensure_space(this);
|
| 2378 |
emit_farith(0xD9, 0xC8, i); |
| 2379 |
} |
| 2380 |
|
| 2381 |
|
| 2382 |
void Assembler::fincstp() {
|
| 2383 |
EnsureSpace ensure_space(this);
|
| 2384 |
emit(0xD9);
|
| 2385 |
emit(0xF7);
|
| 2386 |
} |
| 2387 |
|
| 2388 |
|
| 2389 |
void Assembler::ffree(int i) { |
| 2390 |
EnsureSpace ensure_space(this);
|
| 2391 |
emit_farith(0xDD, 0xC0, i); |
| 2392 |
} |
| 2393 |
|
| 2394 |
|
| 2395 |
void Assembler::ftst() {
|
| 2396 |
EnsureSpace ensure_space(this);
|
| 2397 |
emit(0xD9);
|
| 2398 |
emit(0xE4);
|
| 2399 |
} |
| 2400 |
|
| 2401 |
|
| 2402 |
void Assembler::fucomp(int i) { |
| 2403 |
EnsureSpace ensure_space(this);
|
| 2404 |
emit_farith(0xDD, 0xE8, i); |
| 2405 |
} |
| 2406 |
|
| 2407 |
|
| 2408 |
void Assembler::fucompp() {
|
| 2409 |
EnsureSpace ensure_space(this);
|
| 2410 |
emit(0xDA);
|
| 2411 |
emit(0xE9);
|
| 2412 |
} |
| 2413 |
|
| 2414 |
|
| 2415 |
void Assembler::fucomi(int i) { |
| 2416 |
EnsureSpace ensure_space(this);
|
| 2417 |
emit(0xDB);
|
| 2418 |
emit(0xE8 + i);
|
| 2419 |
} |
| 2420 |
|
| 2421 |
|
| 2422 |
void Assembler::fucomip() {
|
| 2423 |
EnsureSpace ensure_space(this);
|
| 2424 |
emit(0xDF);
|
| 2425 |
emit(0xE9);
|
| 2426 |
} |
| 2427 |
|
| 2428 |
|
| 2429 |
void Assembler::fcompp() {
|
| 2430 |
EnsureSpace ensure_space(this);
|
| 2431 |
emit(0xDE);
|
| 2432 |
emit(0xD9);
|
| 2433 |
} |
| 2434 |
|
| 2435 |
|
| 2436 |
void Assembler::fnstsw_ax() {
|
| 2437 |
EnsureSpace ensure_space(this);
|
| 2438 |
emit(0xDF);
|
| 2439 |
emit(0xE0);
|
| 2440 |
} |
| 2441 |
|
| 2442 |
|
| 2443 |
void Assembler::fwait() {
|
| 2444 |
EnsureSpace ensure_space(this);
|
| 2445 |
emit(0x9B);
|
| 2446 |
} |
| 2447 |
|
| 2448 |
|
| 2449 |
void Assembler::frndint() {
|
| 2450 |
EnsureSpace ensure_space(this);
|
| 2451 |
emit(0xD9);
|
| 2452 |
emit(0xFC);
|
| 2453 |
} |
| 2454 |
|
| 2455 |
|
| 2456 |
void Assembler::fnclex() {
|
| 2457 |
EnsureSpace ensure_space(this);
|
| 2458 |
emit(0xDB);
|
| 2459 |
emit(0xE2);
|
| 2460 |
} |
| 2461 |
|
| 2462 |
|
| 2463 |
void Assembler::sahf() {
|
| 2464 |
// TODO(X64): Test for presence. Not all 64-bit intel CPU's have sahf
|
| 2465 |
// in 64-bit mode. Test CpuID.
|
| 2466 |
EnsureSpace ensure_space(this);
|
| 2467 |
emit(0x9E);
|
| 2468 |
} |
| 2469 |
|
| 2470 |
|
| 2471 |
void Assembler::emit_farith(int b1, int b2, int i) { |
| 2472 |
ASSERT(is_uint8(b1) && is_uint8(b2)); // wrong opcode
|
| 2473 |
ASSERT(is_uint3(i)); // illegal stack offset
|
| 2474 |
emit(b1); |
| 2475 |
emit(b2 + i); |
| 2476 |
} |
| 2477 |
|
| 2478 |
|
| 2479 |
// SSE operations.
|
| 2480 |
|
| 2481 |
void Assembler::andps(XMMRegister dst, XMMRegister src) {
|
| 2482 |
EnsureSpace ensure_space(this);
|
| 2483 |
emit_optional_rex_32(dst, src); |
| 2484 |
emit(0x0F);
|
| 2485 |
emit(0x54);
|
| 2486 |
emit_sse_operand(dst, src); |
| 2487 |
} |
| 2488 |
|
| 2489 |
|
| 2490 |
// SSE 2 operations.
|
| 2491 |
|
| 2492 |
void Assembler::movd(XMMRegister dst, Register src) {
|
| 2493 |
EnsureSpace ensure_space(this);
|
| 2494 |
emit(0x66);
|
| 2495 |
emit_optional_rex_32(dst, src); |
| 2496 |
emit(0x0F);
|
| 2497 |
emit(0x6E);
|
| 2498 |
emit_sse_operand(dst, src); |
| 2499 |
} |
| 2500 |
|
| 2501 |
|
| 2502 |
void Assembler::movd(Register dst, XMMRegister src) {
|
| 2503 |
EnsureSpace ensure_space(this);
|
| 2504 |
emit(0x66);
|
| 2505 |
emit_optional_rex_32(src, dst); |
| 2506 |
emit(0x0F);
|
| 2507 |
emit(0x7E);
|
| 2508 |
emit_sse_operand(src, dst); |
| 2509 |
} |
| 2510 |
|
| 2511 |
|
| 2512 |
void Assembler::movq(XMMRegister dst, Register src) {
|
| 2513 |
EnsureSpace ensure_space(this);
|
| 2514 |
emit(0x66);
|
| 2515 |
emit_rex_64(dst, src); |
| 2516 |
emit(0x0F);
|
| 2517 |
emit(0x6E);
|
| 2518 |
emit_sse_operand(dst, src); |
| 2519 |
} |
| 2520 |
|
| 2521 |
|
| 2522 |
void Assembler::movq(Register dst, XMMRegister src) {
|
| 2523 |
EnsureSpace ensure_space(this);
|
| 2524 |
emit(0x66);
|
| 2525 |
emit_rex_64(src, dst); |
| 2526 |
emit(0x0F);
|
| 2527 |
emit(0x7E);
|
| 2528 |
emit_sse_operand(src, dst); |
| 2529 |
} |
| 2530 |
|
| 2531 |
|
| 2532 |
void Assembler::movq(XMMRegister dst, XMMRegister src) {
|
| 2533 |
EnsureSpace ensure_space(this);
|
| 2534 |
if (dst.low_bits() == 4) { |
| 2535 |
// Avoid unnecessary SIB byte.
|
| 2536 |
emit(0xf3);
|
| 2537 |
emit_optional_rex_32(dst, src); |
| 2538 |
emit(0x0F);
|
| 2539 |
emit(0x7e);
|
| 2540 |
emit_sse_operand(dst, src); |
| 2541 |
} else {
|
| 2542 |
emit(0x66);
|
| 2543 |
emit_optional_rex_32(src, dst); |
| 2544 |
emit(0x0F);
|
| 2545 |
emit(0xD6);
|
| 2546 |
emit_sse_operand(src, dst); |
| 2547 |
} |
| 2548 |
} |
| 2549 |
|
| 2550 |
|
| 2551 |
void Assembler::movdqa(const Operand& dst, XMMRegister src) { |
| 2552 |
EnsureSpace ensure_space(this);
|
| 2553 |
emit(0x66);
|
| 2554 |
emit_rex_64(src, dst); |
| 2555 |
emit(0x0F);
|
| 2556 |
emit(0x7F);
|
| 2557 |
emit_sse_operand(src, dst); |
| 2558 |
} |
| 2559 |
|
| 2560 |
|
| 2561 |
void Assembler::movdqa(XMMRegister dst, const Operand& src) { |
| 2562 |
EnsureSpace ensure_space(this);
|
| 2563 |
emit(0x66);
|
| 2564 |
emit_rex_64(dst, src); |
| 2565 |
emit(0x0F);
|
| 2566 |
emit(0x6F);
|
| 2567 |
emit_sse_operand(dst, src); |
| 2568 |
} |
| 2569 |
|
| 2570 |
|
| 2571 |
void Assembler::movdqu(const Operand& dst, XMMRegister src) { |
| 2572 |
EnsureSpace ensure_space(this);
|
| 2573 |
emit(0xF3);
|
| 2574 |
emit_rex_64(src, dst); |
| 2575 |
emit(0x0F);
|
| 2576 |
emit(0x7F);
|
| 2577 |
emit_sse_operand(src, dst); |
| 2578 |
} |
| 2579 |
|
| 2580 |
|
| 2581 |
void Assembler::movdqu(XMMRegister dst, const Operand& src) { |
| 2582 |
EnsureSpace ensure_space(this);
|
| 2583 |
emit(0xF3);
|
| 2584 |
emit_rex_64(dst, src); |
| 2585 |
emit(0x0F);
|
| 2586 |
emit(0x6F);
|
| 2587 |
emit_sse_operand(dst, src); |
| 2588 |
} |
| 2589 |
|
| 2590 |
|
| 2591 |
void Assembler::extractps(Register dst, XMMRegister src, byte imm8) {
|
| 2592 |
ASSERT(IsEnabled(SSE4_1)); |
| 2593 |
ASSERT(is_uint8(imm8)); |
| 2594 |
EnsureSpace ensure_space(this);
|
| 2595 |
emit(0x66);
|
| 2596 |
emit_optional_rex_32(src, dst); |
| 2597 |
emit(0x0F);
|
| 2598 |
emit(0x3A);
|
| 2599 |
emit(0x17);
|
| 2600 |
emit_sse_operand(src, dst); |
| 2601 |
emit(imm8); |
| 2602 |
} |
| 2603 |
|
| 2604 |
|
| 2605 |
void Assembler::movsd(const Operand& dst, XMMRegister src) { |
| 2606 |
EnsureSpace ensure_space(this);
|
| 2607 |
emit(0xF2); // double |
| 2608 |
emit_optional_rex_32(src, dst); |
| 2609 |
emit(0x0F);
|
| 2610 |
emit(0x11); // store |
| 2611 |
emit_sse_operand(src, dst); |
| 2612 |
} |
| 2613 |
|
| 2614 |
|
| 2615 |
void Assembler::movsd(XMMRegister dst, XMMRegister src) {
|
| 2616 |
EnsureSpace ensure_space(this);
|
| 2617 |
emit(0xF2); // double |
| 2618 |
emit_optional_rex_32(dst, src); |
| 2619 |
emit(0x0F);
|
| 2620 |
emit(0x10); // load |
| 2621 |
emit_sse_operand(dst, src); |
| 2622 |
} |
| 2623 |
|
| 2624 |
|
| 2625 |
void Assembler::movsd(XMMRegister dst, const Operand& src) { |
| 2626 |
EnsureSpace ensure_space(this);
|
| 2627 |
emit(0xF2); // double |
| 2628 |
emit_optional_rex_32(dst, src); |
| 2629 |
emit(0x0F);
|
| 2630 |
emit(0x10); // load |
| 2631 |
emit_sse_operand(dst, src); |
| 2632 |
} |
| 2633 |
|
| 2634 |
|
| 2635 |
void Assembler::movaps(XMMRegister dst, XMMRegister src) {
|
| 2636 |
EnsureSpace ensure_space(this);
|
| 2637 |
if (src.low_bits() == 4) { |
| 2638 |
// Try to avoid an unnecessary SIB byte.
|
| 2639 |
emit_optional_rex_32(src, dst); |
| 2640 |
emit(0x0F);
|
| 2641 |
emit(0x29);
|
| 2642 |
emit_sse_operand(src, dst); |
| 2643 |
} else {
|
| 2644 |
emit_optional_rex_32(dst, src); |
| 2645 |
emit(0x0F);
|
| 2646 |
emit(0x28);
|
| 2647 |
emit_sse_operand(dst, src); |
| 2648 |
} |
| 2649 |
} |
| 2650 |
|
| 2651 |
|
| 2652 |
void Assembler::movapd(XMMRegister dst, XMMRegister src) {
|
| 2653 |
EnsureSpace ensure_space(this);
|
| 2654 |
if (src.low_bits() == 4) { |
| 2655 |
// Try to avoid an unnecessary SIB byte.
|
| 2656 |
emit(0x66);
|
| 2657 |
emit_optional_rex_32(src, dst); |
| 2658 |
emit(0x0F);
|
| 2659 |
emit(0x29);
|
| 2660 |
emit_sse_operand(src, dst); |
| 2661 |
} else {
|
| 2662 |
emit(0x66);
|
| 2663 |
emit_optional_rex_32(dst, src); |
| 2664 |
emit(0x0F);
|
| 2665 |
emit(0x28);
|
| 2666 |
emit_sse_operand(dst, src); |
| 2667 |
} |
| 2668 |
} |
| 2669 |
|
| 2670 |
|
| 2671 |
void Assembler::movss(XMMRegister dst, const Operand& src) { |
| 2672 |
EnsureSpace ensure_space(this);
|
| 2673 |
emit(0xF3); // single |
| 2674 |
emit_optional_rex_32(dst, src); |
| 2675 |
emit(0x0F);
|
| 2676 |
emit(0x10); // load |
| 2677 |
emit_sse_operand(dst, src); |
| 2678 |
} |
| 2679 |
|
| 2680 |
|
| 2681 |
void Assembler::movss(const Operand& src, XMMRegister dst) { |
| 2682 |
EnsureSpace ensure_space(this);
|
| 2683 |
emit(0xF3); // single |
| 2684 |
emit_optional_rex_32(dst, src); |
| 2685 |
emit(0x0F);
|
| 2686 |
emit(0x11); // store |
| 2687 |
emit_sse_operand(dst, src); |
| 2688 |
} |
| 2689 |
|
| 2690 |
|
| 2691 |
void Assembler::cvttss2si(Register dst, const Operand& src) { |
| 2692 |
EnsureSpace ensure_space(this);
|
| 2693 |
emit(0xF3);
|
| 2694 |
emit_optional_rex_32(dst, src); |
| 2695 |
emit(0x0F);
|
| 2696 |
emit(0x2C);
|
| 2697 |
emit_operand(dst, src); |
| 2698 |
} |
| 2699 |
|
| 2700 |
|
| 2701 |
void Assembler::cvttss2si(Register dst, XMMRegister src) {
|
| 2702 |
EnsureSpace ensure_space(this);
|
| 2703 |
emit(0xF3);
|
| 2704 |
emit_optional_rex_32(dst, src); |
| 2705 |
emit(0x0F);
|
| 2706 |
emit(0x2C);
|
| 2707 |
emit_sse_operand(dst, src); |
| 2708 |
} |
| 2709 |
|
| 2710 |
|
| 2711 |
void Assembler::cvttsd2si(Register dst, const Operand& src) { |
| 2712 |
EnsureSpace ensure_space(this);
|
| 2713 |
emit(0xF2);
|
| 2714 |
emit_optional_rex_32(dst, src); |
| 2715 |
emit(0x0F);
|
| 2716 |
emit(0x2C);
|
| 2717 |
emit_operand(dst, src); |
| 2718 |
} |
| 2719 |
|
| 2720 |
|
| 2721 |
void Assembler::cvttsd2si(Register dst, XMMRegister src) {
|
| 2722 |
EnsureSpace ensure_space(this);
|
| 2723 |
emit(0xF2);
|
| 2724 |
emit_optional_rex_32(dst, src); |
| 2725 |
emit(0x0F);
|
| 2726 |
emit(0x2C);
|
| 2727 |
emit_sse_operand(dst, src); |
| 2728 |
} |
| 2729 |
|
| 2730 |
|
| 2731 |
void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
|
| 2732 |
EnsureSpace ensure_space(this);
|
| 2733 |
emit(0xF2);
|
| 2734 |
emit_rex_64(dst, src); |
| 2735 |
emit(0x0F);
|
| 2736 |
emit(0x2C);
|
| 2737 |
emit_sse_operand(dst, src); |
| 2738 |
} |
| 2739 |
|
| 2740 |
|
| 2741 |
void Assembler::cvtlsi2sd(XMMRegister dst, const Operand& src) { |
| 2742 |
EnsureSpace ensure_space(this);
|
| 2743 |
emit(0xF2);
|
| 2744 |
emit_optional_rex_32(dst, src); |
| 2745 |
emit(0x0F);
|
| 2746 |
emit(0x2A);
|
| 2747 |
emit_sse_operand(dst, src); |
| 2748 |
} |
| 2749 |
|
| 2750 |
|
| 2751 |
void Assembler::cvtlsi2sd(XMMRegister dst, Register src) {
|
| 2752 |
EnsureSpace ensure_space(this);
|
| 2753 |
emit(0xF2);
|
| 2754 |
emit_optional_rex_32(dst, src); |
| 2755 |
emit(0x0F);
|
| 2756 |
emit(0x2A);
|
| 2757 |
emit_sse_operand(dst, src); |
| 2758 |
} |
| 2759 |
|
| 2760 |
|
| 2761 |
void Assembler::cvtlsi2ss(XMMRegister dst, Register src) {
|
| 2762 |
EnsureSpace ensure_space(this);
|
| 2763 |
emit(0xF3);
|
| 2764 |
emit_optional_rex_32(dst, src); |
| 2765 |
emit(0x0F);
|
| 2766 |
emit(0x2A);
|
| 2767 |
emit_sse_operand(dst, src); |
| 2768 |
} |
| 2769 |
|
| 2770 |
|
| 2771 |
void Assembler::cvtqsi2sd(XMMRegister dst, Register src) {
|
| 2772 |
EnsureSpace ensure_space(this);
|
| 2773 |
emit(0xF2);
|
| 2774 |
emit_rex_64(dst, src); |
| 2775 |
emit(0x0F);
|
| 2776 |
emit(0x2A);
|
| 2777 |
emit_sse_operand(dst, src); |
| 2778 |
} |
| 2779 |
|
| 2780 |
|
| 2781 |
void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
|
| 2782 |
EnsureSpace ensure_space(this);
|
| 2783 |
emit(0xF3);
|
| 2784 |
emit_optional_rex_32(dst, src); |
| 2785 |
emit(0x0F);
|
| 2786 |
emit(0x5A);
|
| 2787 |
emit_sse_operand(dst, src); |
| 2788 |
} |
| 2789 |
|
| 2790 |
|
| 2791 |
void Assembler::cvtss2sd(XMMRegister dst, const Operand& src) { |
| 2792 |
EnsureSpace ensure_space(this);
|
| 2793 |
emit(0xF3);
|
| 2794 |
emit_optional_rex_32(dst, src); |
| 2795 |
emit(0x0F);
|
| 2796 |
emit(0x5A);
|
| 2797 |
emit_sse_operand(dst, src); |
| 2798 |
} |
| 2799 |
|
| 2800 |
|
| 2801 |
void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
|
| 2802 |
EnsureSpace ensure_space(this);
|
| 2803 |
emit(0xF2);
|
| 2804 |
emit_optional_rex_32(dst, src); |
| 2805 |
emit(0x0F);
|
| 2806 |
emit(0x5A);
|
| 2807 |
emit_sse_operand(dst, src); |
| 2808 |
} |
| 2809 |
|
| 2810 |
|
| 2811 |
void Assembler::cvtsd2si(Register dst, XMMRegister src) {
|
| 2812 |
EnsureSpace ensure_space(this);
|
| 2813 |
emit(0xF2);
|
| 2814 |
emit_optional_rex_32(dst, src); |
| 2815 |
emit(0x0F);
|
| 2816 |
emit(0x2D);
|
| 2817 |
emit_sse_operand(dst, src); |
| 2818 |
} |
| 2819 |
|
| 2820 |
|
| 2821 |
void Assembler::cvtsd2siq(Register dst, XMMRegister src) {
|
| 2822 |
EnsureSpace ensure_space(this);
|
| 2823 |
emit(0xF2);
|
| 2824 |
emit_rex_64(dst, src); |
| 2825 |
emit(0x0F);
|
| 2826 |
emit(0x2D);
|
| 2827 |
emit_sse_operand(dst, src); |
| 2828 |
} |
| 2829 |
|
| 2830 |
|
| 2831 |
void Assembler::addsd(XMMRegister dst, XMMRegister src) {
|
| 2832 |
EnsureSpace ensure_space(this);
|
| 2833 |
emit(0xF2);
|
| 2834 |
emit_optional_rex_32(dst, src); |
| 2835 |
emit(0x0F);
|
| 2836 |
emit(0x58);
|
| 2837 |
emit_sse_operand(dst, src); |
| 2838 |
} |
| 2839 |
|
| 2840 |
|
| 2841 |
void Assembler::addsd(XMMRegister dst, const Operand& src) { |
| 2842 |
EnsureSpace ensure_space(this);
|
| 2843 |
emit(0xF2);
|
| 2844 |
emit_optional_rex_32(dst, src); |
| 2845 |
emit(0x0F);
|
| 2846 |
emit(0x58);
|
| 2847 |
emit_sse_operand(dst, src); |
| 2848 |
} |
| 2849 |
|
| 2850 |
|
| 2851 |
void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
|
| 2852 |
EnsureSpace ensure_space(this);
|
| 2853 |
emit(0xF2);
|
| 2854 |
emit_optional_rex_32(dst, src); |
| 2855 |
emit(0x0F);
|
| 2856 |
emit(0x59);
|
| 2857 |
emit_sse_operand(dst, src); |
| 2858 |
} |
| 2859 |
|
| 2860 |
|
| 2861 |
void Assembler::mulsd(XMMRegister dst, const Operand& src) { |
| 2862 |
EnsureSpace ensure_space(this);
|
| 2863 |
emit(0xF2);
|
| 2864 |
emit_optional_rex_32(dst, src); |
| 2865 |
emit(0x0F);
|
| 2866 |
emit(0x59);
|
| 2867 |
emit_sse_operand(dst, src); |
| 2868 |
} |
| 2869 |
|
| 2870 |
|
| 2871 |
void Assembler::subsd(XMMRegister dst, XMMRegister src) {
|
| 2872 |
EnsureSpace ensure_space(this);
|
| 2873 |
emit(0xF2);
|
| 2874 |
emit_optional_rex_32(dst, src); |
| 2875 |
emit(0x0F);
|
| 2876 |
emit(0x5C);
|
| 2877 |
emit_sse_operand(dst, src); |
| 2878 |
} |
| 2879 |
|
| 2880 |
|
| 2881 |
void Assembler::divsd(XMMRegister dst, XMMRegister src) {
|
| 2882 |
EnsureSpace ensure_space(this);
|
| 2883 |
emit(0xF2);
|
| 2884 |
emit_optional_rex_32(dst, src); |
| 2885 |
emit(0x0F);
|
| 2886 |
emit(0x5E);
|
| 2887 |
emit_sse_operand(dst, src); |
| 2888 |
} |
| 2889 |
|
| 2890 |
|
| 2891 |
void Assembler::andpd(XMMRegister dst, XMMRegister src) {
|
| 2892 |
EnsureSpace ensure_space(this);
|
| 2893 |
emit(0x66);
|
| 2894 |
emit_optional_rex_32(dst, src); |
| 2895 |
emit(0x0F);
|
| 2896 |
emit(0x54);
|
| 2897 |
emit_sse_operand(dst, src); |
| 2898 |
} |
| 2899 |
|
| 2900 |
|
| 2901 |
void Assembler::orpd(XMMRegister dst, XMMRegister src) {
|
| 2902 |
EnsureSpace ensure_space(this);
|
| 2903 |
emit(0x66);
|
| 2904 |
emit_optional_rex_32(dst, src); |
| 2905 |
emit(0x0F);
|
| 2906 |
emit(0x56);
|
| 2907 |
emit_sse_operand(dst, src); |
| 2908 |
} |
| 2909 |
|
| 2910 |
|
| 2911 |
void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
|
| 2912 |
EnsureSpace ensure_space(this);
|
| 2913 |
emit(0x66);
|
| 2914 |
emit_optional_rex_32(dst, src); |
| 2915 |
emit(0x0F);
|
| 2916 |
emit(0x57);
|
| 2917 |
emit_sse_operand(dst, src); |
| 2918 |
} |
| 2919 |
|
| 2920 |
|
| 2921 |
void Assembler::xorps(XMMRegister dst, XMMRegister src) {
|
| 2922 |
EnsureSpace ensure_space(this);
|
| 2923 |
emit_optional_rex_32(dst, src); |
| 2924 |
emit(0x0F);
|
| 2925 |
emit(0x57);
|
| 2926 |
emit_sse_operand(dst, src); |
| 2927 |
} |
| 2928 |
|
| 2929 |
|
| 2930 |
void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
|
| 2931 |
EnsureSpace ensure_space(this);
|
| 2932 |
emit(0xF2);
|
| 2933 |
emit_optional_rex_32(dst, src); |
| 2934 |
emit(0x0F);
|
| 2935 |
emit(0x51);
|
| 2936 |
emit_sse_operand(dst, src); |
| 2937 |
} |
| 2938 |
|
| 2939 |
|
| 2940 |
void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
|
| 2941 |
EnsureSpace ensure_space(this);
|
| 2942 |
emit(0x66);
|
| 2943 |
emit_optional_rex_32(dst, src); |
| 2944 |
emit(0x0f);
|
| 2945 |
emit(0x2e);
|
| 2946 |
emit_sse_operand(dst, src); |
| 2947 |
} |
| 2948 |
|
| 2949 |
|
| 2950 |
void Assembler::ucomisd(XMMRegister dst, const Operand& src) { |
| 2951 |
EnsureSpace ensure_space(this);
|
| 2952 |
emit(0x66);
|
| 2953 |
emit_optional_rex_32(dst, src); |
| 2954 |
emit(0x0f);
|
| 2955 |
emit(0x2e);
|
| 2956 |
emit_sse_operand(dst, src); |
| 2957 |
} |
| 2958 |
|
| 2959 |
|
| 2960 |
void Assembler::cmpltsd(XMMRegister dst, XMMRegister src) {
|
| 2961 |
EnsureSpace ensure_space(this);
|
| 2962 |
emit(0xF2);
|
| 2963 |
emit_optional_rex_32(dst, src); |
| 2964 |
emit(0x0F);
|
| 2965 |
emit(0xC2);
|
| 2966 |
emit_sse_operand(dst, src); |
| 2967 |
emit(0x01); // LT == 1 |
| 2968 |
} |
| 2969 |
|
| 2970 |
|
| 2971 |
void Assembler::roundsd(XMMRegister dst, XMMRegister src,
|
| 2972 |
Assembler::RoundingMode mode) {
|
| 2973 |
ASSERT(IsEnabled(SSE4_1)); |
| 2974 |
EnsureSpace ensure_space(this);
|
| 2975 |
emit(0x66);
|
| 2976 |
emit_optional_rex_32(dst, src); |
| 2977 |
emit(0x0f);
|
| 2978 |
emit(0x3a);
|
| 2979 |
emit(0x0b);
|
| 2980 |
emit_sse_operand(dst, src); |
| 2981 |
// Mask precision exeption.
|
| 2982 |
emit(static_cast<byte>(mode) | 0x8); |
| 2983 |
} |
| 2984 |
|
| 2985 |
|
| 2986 |
void Assembler::movmskpd(Register dst, XMMRegister src) {
|
| 2987 |
EnsureSpace ensure_space(this);
|
| 2988 |
emit(0x66);
|
| 2989 |
emit_optional_rex_32(dst, src); |
| 2990 |
emit(0x0f);
|
| 2991 |
emit(0x50);
|
| 2992 |
emit_sse_operand(dst, src); |
| 2993 |
} |
| 2994 |
|
| 2995 |
|
| 2996 |
void Assembler::movmskps(Register dst, XMMRegister src) {
|
| 2997 |
EnsureSpace ensure_space(this);
|
| 2998 |
emit_optional_rex_32(dst, src); |
| 2999 |
emit(0x0f);
|
| 3000 |
emit(0x50);
|
| 3001 |
emit_sse_operand(dst, src); |
| 3002 |
} |
| 3003 |
|
| 3004 |
|
| 3005 |
void Assembler::emit_sse_operand(XMMRegister reg, const Operand& adr) { |
| 3006 |
Register ireg = { reg.code() };
|
| 3007 |
emit_operand(ireg, adr); |
| 3008 |
} |
| 3009 |
|
| 3010 |
|
| 3011 |
void Assembler::emit_sse_operand(XMMRegister dst, XMMRegister src) {
|
| 3012 |
emit(0xC0 | (dst.low_bits() << 3) | src.low_bits()); |
| 3013 |
} |
| 3014 |
|
| 3015 |
|
| 3016 |
void Assembler::emit_sse_operand(XMMRegister dst, Register src) {
|
| 3017 |
emit(0xC0 | (dst.low_bits() << 3) | src.low_bits()); |
| 3018 |
} |
| 3019 |
|
| 3020 |
|
| 3021 |
void Assembler::emit_sse_operand(Register dst, XMMRegister src) {
|
| 3022 |
emit(0xC0 | (dst.low_bits() << 3) | src.low_bits()); |
| 3023 |
} |
| 3024 |
|
| 3025 |
|
| 3026 |
void Assembler::db(uint8_t data) {
|
| 3027 |
EnsureSpace ensure_space(this);
|
| 3028 |
emit(data); |
| 3029 |
} |
| 3030 |
|
| 3031 |
|
| 3032 |
void Assembler::dd(uint32_t data) {
|
| 3033 |
EnsureSpace ensure_space(this);
|
| 3034 |
emitl(data); |
| 3035 |
} |
| 3036 |
|
| 3037 |
|
| 3038 |
// Relocation information implementations.
|
| 3039 |
|
| 3040 |
void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
|
| 3041 |
ASSERT(!RelocInfo::IsNone(rmode)); |
| 3042 |
if (rmode == RelocInfo::EXTERNAL_REFERENCE) {
|
| 3043 |
// Don't record external references unless the heap will be serialized.
|
| 3044 |
#ifdef DEBUG
|
| 3045 |
if (!Serializer::enabled()) {
|
| 3046 |
Serializer::TooLateToEnableNow(); |
| 3047 |
} |
| 3048 |
#endif
|
| 3049 |
if (!Serializer::enabled() && !emit_debug_code()) {
|
| 3050 |
return;
|
| 3051 |
} |
| 3052 |
} else if (rmode == RelocInfo::CODE_AGE_SEQUENCE) { |
| 3053 |
// Don't record psuedo relocation info for code age sequence mode.
|
| 3054 |
return;
|
| 3055 |
} |
| 3056 |
RelocInfo rinfo(pc_, rmode, data, NULL);
|
| 3057 |
reloc_info_writer.Write(&rinfo); |
| 3058 |
} |
| 3059 |
|
| 3060 |
|
| 3061 |
void Assembler::RecordJSReturn() {
|
| 3062 |
positions_recorder()->WriteRecordedPositions(); |
| 3063 |
EnsureSpace ensure_space(this);
|
| 3064 |
RecordRelocInfo(RelocInfo::JS_RETURN); |
| 3065 |
} |
| 3066 |
|
| 3067 |
|
| 3068 |
void Assembler::RecordDebugBreakSlot() {
|
| 3069 |
positions_recorder()->WriteRecordedPositions(); |
| 3070 |
EnsureSpace ensure_space(this);
|
| 3071 |
RecordRelocInfo(RelocInfo::DEBUG_BREAK_SLOT); |
| 3072 |
} |
| 3073 |
|
| 3074 |
|
| 3075 |
void Assembler::RecordComment(const char* msg, bool force) { |
| 3076 |
if (FLAG_code_comments || force) {
|
| 3077 |
EnsureSpace ensure_space(this);
|
| 3078 |
RecordRelocInfo(RelocInfo::COMMENT, reinterpret_cast<intptr_t>(msg));
|
| 3079 |
} |
| 3080 |
} |
| 3081 |
|
| 3082 |
|
| 3083 |
const int RelocInfo::kApplyMask = RelocInfo::kCodeTargetMask | |
| 3084 |
1 << RelocInfo::RUNTIME_ENTRY |
|
| 3085 |
1 << RelocInfo::INTERNAL_REFERENCE |
|
| 3086 |
1 << RelocInfo::CODE_AGE_SEQUENCE;
|
| 3087 |
|
| 3088 |
|
| 3089 |
bool RelocInfo::IsCodedSpecially() {
|
| 3090 |
// The deserializer needs to know whether a pointer is specially coded. Being
|
| 3091 |
// specially coded on x64 means that it is a relative 32 bit address, as used
|
| 3092 |
// by branch instructions.
|
| 3093 |
return (1 << rmode_) & kApplyMask; |
| 3094 |
} |
| 3095 |
|
| 3096 |
} } // namespace v8::internal
|
| 3097 |
|
| 3098 |
#endif // V8_TARGET_ARCH_X64 |